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In this work, polarity dependent of gate oxide breakdown is investigated for both NMOS and PMOS in a large range of oxide thicknesses, 27Å, 170Å and 850Å. All the devices are measured using constant voltage stress (CVS) method. From the measurements, It is found that for thick gate oxide, lifetime (TBD) under negative gate bias is always shorter regardless of the types of the MOSFETs. However, when...
In this talk, I will review our study of graphene electronics and photonics. I will begin by discussing the merits of graphene for particular applications in electronics, optoelectronics and plasmonics. Then, I will elaborate on our understanding of their basic device physics and technological challenges, through theory, modeling and experiments.
In this paper, a data converter for current signal with temperature-compensated sampled resistor implemented in a mixed-signal CMOS process is presented. This circuit is suitable for the current signal processing very much since the low temperature coefficient resistor is integrated in a single chip. It operates with the single power supply of +5V. Experimental results show that the sample resistor...
In this paper two kinds of three-dimensional (3D) on-chip inductor structures based on through-silicon vias (TSVs) are presented, which are quite suitable for applications in 3D integrated circuits. Their electromagnetic characteristics are analyzed by full-wave electromagnetic simulations and compared to those of planar spiral inductors. The results reveal that the 3D inductors based on TSVs have...
In this paper, variations of device parameters, such as threshold voltage (Vth) and saturation current (Idsat), of the devices with and without dog-bone-shaped active-area are investigated with a set of test structures in both 65nm and 40nm CMOS technology processes, respectively. The experiments show that variations of Vth/Idsat of dog-bone devices are more serious than the non-dog-bone device. At...
We propose a novel algorithm for inverse quantization in some audio codec systems, such as MP3, AAC, etc. The optimized algorithm not only reduces the memory size and increases the accuracy of coefficients, but also simplifies the calculations. Compared with other reported algorithms based on float-point calculation, the novel method significantly improved both the accuracy and calculation complexity...
In this work, silicon-based MEMs capacitive microphone was designed and fabricated on 150mm CMOS Line. 400um thin wafer was used as starting wafer, which can greatly reduce process integration complexity accompany with the reduced cost. Low-stress poly film was used as back-plate and membrane. CMOS BEOL Al film was used as PAD for the back-plate and membrane. To make better control of wafer bowing...
Design of 14 nm bulk FinFET is discussed and some properties are analyzed physically. The source/drain junction depth is the most important parameter to reduce off-current, and a punchthrough barrier of a peak concentration higher than ∼2×1018 cm−3 should be formed just underneath the junction depth at the same time. Uniform body doping concentration needs to be designed to have a doping in the range...
In this paper, we study the impact of stress effect on n-MOSFET characteristics, from neighborhood device active area (NDAA) and surrounding shallow trench isolation (SSTI), in addition to the stress from its own active area (AA) and shallow trench isolation (STI). With a group of test structures at a 40nm technology, measurement data are performed and analyzed to understand the impacts of the neighbor...
This paper presents an equalization system for 2 series-connected Li-ion batteries. The voltages of the 2 series-connected Li-ion batteries are measured by the monitor circuit. The voltages are compared through the comparison circuit. According to the result of the comparison circuit, the control circuit determines the equalization circuit that is switched on or off so as to realize the equalization...
This paper represents a Time-to-digital Converter (TDC) architecture based in a FPGA. The proposed architecture relies on a single tapped-delay line to implement time-to-digital conversion, taking advantage of the fast dedicated carry chains available within FPGAs. The results of post-route simulation indicate that this architecture offered a time resolution of 34ps with a 12 ps precision. In a Virtex-4...
A high performance bulk floating body memory device is demonstrated in this work. Experimental results show a data retention of 1.89s and a initial memory window over 60µA@85°C, which are excellent features for eDRAM application. A novel read method based on parasitic BJT effect is introduced to improve device performance. The impact of process parameters is investigated and P well doping is found...
Ag dendrite formed on the Cu pyramids was fabricated as the SERS substrate by wet etching of Si, magnetron sputtering and galvanic displacement process. A flat sample with Ag dendrite on Cu film was prepared as a reference. The SEM results show that the Ag dendrite structure formed on the Cu pyramids exhibits much larger surface area and more nanoparticles and gaps than the flat one. Rhodamine 6G...
A novel scaling theory for fully-depleted omega-gate (ΩG) MOSFETs including rectangular-shaped ΩG (RΩG) and cylindrical-shaped ΩG (CΩG) FETs is presented. The natural length for ΩG MOSFET is obtained by the equation of equivalent number of gates (ENG), where the ΩG device can be virtually broken into equivalent double-gate (DG) and single-gate (SG) transistors working in parallel based on perimeter-weighted-sum...
This pager discusses an open source standard cell library of partially deplete Silicon-on-Insulator (PD-SOI) for use in nanometer PD-SOI research and education. The library includes both front end and back end for SOI digital integrated circuit (IC) design. The BSIMSOI level 10 model used in this study has been verified with the experimental data of a 45nm standard SOI process. The PD-SOI technology...
An accurate yet fast approach is developed to calculate the 2D coupling capacitance between the through silicon via (TSV) and horizontal interconnect wire in 3D IC. We consider the realistic cylinder shape of TSV, and derive the analytical formulas utilizing the idea of field-based analysis. To improve the accuracy, theoretical and numerical results are used to calibrate the formulas. The proposed...
In this paper, a collision and tag number detector for Radio Frequency Identification (RFID) reader is introduced. In EPC Gen2 protocol, Frame Slotted Aloha (FSA) is applied for mu lti-tag anti-co llision. In some state-of-the-art researches, collision recovery methods are developed to turn a collision slot into a successful slot. To reduce failing recovery, the reader needs to know if there is collision...
A power-constrained contrast enhancement algorithm is proposed for high contrast low power active-matrix organic light-emitting diode (AMOLED) display. The contrast enhancement and power constraint are implemented respectively for each histogram segment. The proposed algorithm is simple in order to be implemented into the hardware. Simulation results demonstrate that the proposed algorithm can reduce...
In recent years, with the development of Wireless Body Area Network (WBAN), it has become the key technology which can be used in many medical and non-medical applications. The design of a low noise amplifier which is applied to the body-channel communication (BCC) is presented in this paper. It adopts TSMC RF CMOS 0.18µm process. Parallel resistor's negative feedback structure and noise cancellation...
Based on dynamic element matching (DEM) and pseudorandom noise (PN), a digital background calibration scheme, applicable to mu ltistage pipelined analog-to-digital converters (PADCs), to correct the linearity errors resulting from capacitance mismatches is presented. This calibration technique scheme takes advantage of the PN sequence to extract linearity errors and DEM to make sure the errors of...
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