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An ultra-thin, flexible package was successfully demonstrated in this paper. The integration of semiconductor chip and flexible substrate, development of ultra-thin chip technology, and embedded chip technology are the key topics. For the purpose of bendable, the embedded chip should be thin enough. The chips were thinned to less than 20 mum by mechanical grinding and plasma treatment process. Besides,...
This paper discloses an ultra-thin and highly flexible package with embedded active chips. In this structure, there are no any supporting and permanent substrates needed. A 3 um copper foil with 18 um carrier layer was used as temporal substrate. The carrier layer will be removed after chip embedded process. After patterning and etching processes, the temporal copper foil became the bottom circuit...
Previously, the electronics devices are always integrated into a rigid substrate. Itpsilas stronger, but hardly compatible with Bio-tech or some implanted systems for human being whose packaging point should be more focusing on the flexibility or even the stretchability. Not only the packaging of the active devices but also the connections among them need to be more flexible. In other words, as to...
This paper brings into light a new ultra-thin and highly flexible package with embedded active chips. In this technology, no supporting and permanent substrates were needed. Copper foil was used as temporal substrate, and it became the bottom circuit after patterning and etching processes. Ultra-thin chips with 20~25 mum thickness were assembled directly on the structured copper foils in a flip-chip...
In order to achieve the shorter circuit design of multiple chips, three-dimensional (3D) packaging technologies with through silicon vias were developed to achieve high performance, low power consumption and small packaging size. In this paper, a PCB (Printed Circuit Board) processing compatible structure of three-dimensional chip stacking with low cost and easy fabrication will be shown. 3D and through...
Wafer level chip stacked module by embedded IC packaging technology was studied in this paper. Wafers were treated to less than 50 mum thickness and then singulated. The prepared thin chips were stacked on to the base wafer and then embedded by dielectric layers (Ajinomoto build up film, ABF) lamination. Vias to both the pads on the analog chips and digital wafers were done by UV laser drilling process...
By properly incorporating wafer level package (WLP) and chip embedded processes, a type II chip-in-substrate package (CiSP) without ultra-thin chips is developed for high speed memory devices in this paper. According to the design concept of the type II CiSP, a hybrid process using build-up technologies in wafer level and COG-based (chip-on-glass) transfer bonding is explored to implement the JEDEC-compliant...
In this paper, chip to wafer stacking and embedding active components by wafer level technologies were described. The radio frequency (RF) module-like component was chosen as the test vehicle in this study. Analog wafer were treated to less than 50 mum thickness and then singulated. The thin chip were die bonded, by chip stacking method, on to the digital wafer and embedded by lamination of dielectric...
The paper describes the newly development technology of 3D stacking packaging by introducing laser-drilled through silicon interconnect (LTSI). Compared to the recently abundant researches of 3D chip-to-wafer or wafer-to-wafer stacking, it demonstrated a more reliable and practical process flow to achieve the 3D stacking technology. The investigation of thermal effect and electrical properties on...
Chip-in-substrate package (CiSP) is an embedded active device packaging technology. In this research, DDRII memory was chosen as the CiSP test vehicle. Several techniques were well developed to achieve CiSP with high yield and good reliability. The vehicle was tested by lead-free reliability tests, inclusive of pre-condition level-3 (3 reflows at 260degC), level B thermal cycle, 168 hrs pressure cooker,...
Flat panel displays (FPDs) are now getting more important role in the application of digital home and personal consumer electronics. For the future mobile application, the lack of flexibility and the decrement of weight will become the major challenges by using the glass substrate. The new choice of substrate material can provide the benefits to make the display become flexible that the current glass...
Abundant three-dimensional packaging technologies were developed for chip-to-wafer or wafer-to-wafer bonding, which employed through silicon interconnect to achieve the shortest circuit design of inter-chip or inter-wafer. In this paper, we focused on the wafer stacking technology by introducing silicon-through three-dimensional interconnect. The innovative structure as shown here is a new concept...
As the demands for high-density, high-speed, high-performance, and multi-function in portable electronic products, packaging technologies require significant improvement to bring out ICs' performance and shrink the total module or package size. One representative technology is to embed active devices into an organic substrate by sequential build-up processes, for example, chip-in-polymer by IZM, bumpless...
We developed an optical sub-assembly (OSA) module for a four-channel coarse wavelength division multiplexing (CWDM) transceiver that satisfied the size requirement for XENPAK, X2 and XPAK multisource agreement (MSA). This module is composed of a frame structure with compact star-shaped optics paths, die-on-header laser or photodetector, thin film filters, ball lens and SC receptacle. The star-shaped...
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