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In this work, the authors demonstrate Core-type and IO-type on-die noise characterization to enhance CPU PDN (Power Delivery Network) performance in microprocessor. The two representative power supply noise characteristics are simulated using excitation models and an impedance modeled of the power delivery network. Then, the design metrics for the PDN are analyzed based on excitation. Behavior of...
This paper presents an in-depth study on how the magnitude of simultaneous switching output (SSO) noise is affected by on-chip supply grid resistances. A key observation of the study is that under certain circumstances, increasing the resistance of certain parts of a supply grid can be very effective in reducing SSO noise, and the gain from SSO noise reduction can significantly outweigh the resulted...
This paper reports on modeling of simultaneous switching noise (SSN) in power distribution network (PDN) for 3D systems, where multiple IC chips are stacked and connected by through-silicon vias (TSVs). The noises generated by current switching during the transition from idle state to active state are analyzed with both on-chip and off-chip PDNs. SSN is decomposed into different frequency components...
Power supply induced clock jitter accumulation is a function of several variables including the power supply rejection characteristics of circuits in the signal path, signal path electrical length, signaling frequency, and voltage supply noise magnitude and frequency. Brute force, closed-loop, transistor-level modeling and simulation of clock timing in the presence of an extracted power delivery network...
Increase in power density and decrease in supply voltage results in greater power supply current. With scaling, line resistance increases. Together with increase in supply current, this results in ever larger IR drop in supply voltage. IR drop analysis is an important element of power supply network design. Maximizing IR drop is also an important component of manufacturing testing. As a CMOS gate...
This paper introduces the detrimental effects of voltage regulator noise on ΔVBE-based temperature sense circuits. The work began when a significant temperature reporting inaccuracy was observed on a commercial DC-DC power conversion module. In the paper, the observed problem will be discussed, and a Spice model presented which allows the issue to be simulated. The main part of the work, however,...
Low power LNA design for high frequency wireless application is one of the challenging tasks in present scenario of VLSI. The major components of noise in amplifier are incorporated into flicker noise and thermal noise. In this paper the main concentration is given on a comparative study for a single ended LNA in the platform of 130nm to 22nm models of BSIM4 series and Verilog based CNTFET. Nose figure,...
A generalized terminal modeling technique was proposed earlier to predict conducted electromagnetic interference from a dc-dc boost converter. This paper extends the generalized terminal modeling approach to converters with the buck-type input. The technique is developed for the electromagnetic interference modeling of switched power converters in aerospace applications where the requirements on electromagnetic...
When a single bit is flipped as a result of a transient error in an electronic circuit, its effect can have a severe impact if the circuit is deployed in safety critical domains such as automotive, aeronautics, and industrial automation. In the design phase it is therefore essential to evaluate, and where necessary improve, the resilience of a circuit to all possible transient errors. In this paper,...
The paper describes an approach for semi-symbolic analysis of mixed-signal systems that contain discontinuous functions, e.g. due to modeling comparators. For modeling and semi-symbolic simulation, we use extended Affine Arithmetic. Affine Arithmetic is currently limited to accurate analysis of linear functions and mild non-linear functions, but not yet discontinuities. In this paper we extend the...
A common mode choke coil (CMC) is mounted on the differential signal lines to suppress common mode noise propagating on differential signal lines. To evaluate the noise suppression effect of the CMC in the design phase of the equipments, 3D electromagnetic simulation considering the physical structure of the circuit, such as the pattern layout of the printed circuit board and inter connection, should...
We analyzed equivalent current source of cryptographic circuits implemented on a field programmable gate array (FPGA). The equivalent current source represented internal switching current behaviors in the cryptographic circuits during an Advanced Encryption Standard (AES) operation. In this work, the internal current was analyzed for extracting leakage functions and correlation coefficients from scatter...
Finding a suitable topology and Noise-transfer-function for higher order Incremental Delta-Sigma ADCs is a complex task. Estimating the performance of the ADC taking the circuit nonidealities into account by simulation requires sophisticated modeling and significant computing resources. Even with complex models, taking into account all nonidealities is not possible. This work proposes a completely...
The increasing demand for electronic devices and circuits dedicated to harsh environment applications, specifically high temperature and high power, has called for more research dedicated towards silicon carbide (SiC) devices and integrated circuits (ICs). SiC, a wide bandgap semiconductor, is inherently capable of operation in such environments. SiC bipolar transistors unlike MOSFETs, do not have...
A new design procedure is derived for analog design with MOSTs in all three regions of operation i.e. strong and weak inversion and velocity saturation. BSIM6/EKV model parameters are used. Optimum biasing points are derived for single- and two-stage amplifiers. It is shown that for channel lengths around 20 nm, a unique optimum is achieved for the fT × gm/IDS Figure of merit. At such low channel...
In a spacecraft, the Electro Explosive Devices (EED) are used for the appendages deployment activities like Antennas Deployment, Solar arrays deployment etc. EED electronics package provides the required excitation to fire the SQUIB. During the launch phase, the spacecraft experiences a high level of Electromagnetic (EM) radiation. The EEDs should not get enabled due to the EM radiation. EMC analysis...
In the proposed work, crosstalk effects are investigated in two identically coupled SWCNT bundle interconnects at 21 nm and 15 nm technology nodes for intermediate and global interconnects. An ABCD parameter based approach has been used to investigate crosstalk delay and noise in both sparse and dense SWCNT bundle interconnect system. The simulation results show that the proposed model is not only...
This paper proposes a PDN design method using frequency-dependent target impedance considering frequency properties of jitter sensitivity of the IO buffer to power supply noise and switching current profile. We confirmed that this design and the resulting jitter of the I/O interface attributable to power supply noise meet the target value of less than 5 %UI.
Power integrity design has become a critical issue in digital electronic systems, as advanced CMOS LSIs operate at higher clock frequency and at lower supply voltage. Power supply fluctuation excited by core circuits or I/O buffer circuits induces logic instability and electromagnetic radiation. Therefore, total impedance of power distribution network (PDN) must be taking into consideration in the...
A potential technology by silicon interposer enables high bandwidth and low power application processing devices of the future, because the demand of smart mobile products are driving for higher logic-to-memory bandwidth (BW) over 30 GB/s with lower power consumption and ultra-memory capacity. This paper presents a 2.5D-IC structure with silicon interposer to demonstrate electrical performances including...
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