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This paper presents a four-level pulse amplitude modulation (4-PAM) memory I/O interface for 3D stacked DRAMs. 3D integration technology is a promising solution for higher bandwidth and less power consumption due to the shortened link distance. The proposed transceiver is designed for 3D interconnects. The proposed transmitter employs a current mode output driver which sends data through TSVs. The...
We present the architecture of and measured results for ULSNAP: a fully-implemented ultra-low power event-driven microcontroller targeted at the bursty workloads of the sensor network application space. ULSNAP is event-driven at both the microarchitectural and circuit levels in order to minimize static power, energy per operation, and wake up energy while maximizing performance. Our 90nm test chip...
In timing signoff for leading-edge SOCs, even few-picosecond timing violations will not only increase design turnaround time, but also degrade design quality (e.g., through power increase from insertion of extra buffers). Conventional flip-flop timing models have fixed values of setup/hold times and clock-to-q (c2q) delay, with some advanced “setup-hold pessimism reduction” (SHPR) methodologies exploiting...
Useful skew is a well-known design technique that adjusts clock sink latencies to improve performance and/or robustness of highperformance IC designs. Current design methodologies apply useful skew after the netlist has been synthesized (e.g., with a uniform skew or clock uncertainty assumption on all flops), and after placement has been performed. However, the useful skew optimization is constrained...
This paper presents the design, simulation, bench measurement and long-term reliability test results of a drift-resistant clock generator. Designed for applications at a stable body temperature with a lifelong operating expectancy, this clock design uses multiple design techniques to minimize the long-term performance degradation and results in a clock circuit with superior frequency stability. This...
This paper presents a topology-optimized passive thermal micro actuator with large thermal deflection. The actuator relies on different coefficients of thermal expansion of an active material as well as the substrate and temperature changes of the surrounding environment. COMSOL Multiphysics is used for the topology optimization algorithm. The resulting shape is approximated by straight beams for...
Increase in power density and decrease in supply voltage results in greater power supply current. With scaling, line resistance increases. Together with increase in supply current, this results in ever larger IR drop in supply voltage. IR drop analysis is an important element of power supply network design. Maximizing IR drop is also an important component of manufacturing testing. As a CMOS gate...
We propose, for the first time, the use of hierarchical matrix (H-matrix) in the efficient finite-element-based (FE-based) direct solver implementation for both steady and transient thermal analyses of three-dimensional integrated circuits (3D ICs). H-matrix was shown to provide a data-sparse way to approximate the matrices and their inverses with almost linear space and time complexities. We show...
The design of MPSoCs is a complex task. From the designer side point of view, a new feature inserted into the system (e.g. a mapping heuristic or a new function in the operating system) must be validated with a large set of the MPSoC configurations. From the application developer side point of view, the performance of a set of applications running simultaneously in the MPSoC platform must be also...
Embedded systems require even more flexibility. Several system permits on-the-market software updates. However these updates must be reliable, otherwise, the results can be catastrophic. Device drivers may have any updates and they are very vulnerable to this problem, requiring mechanisms that are able to capture errors arising from updates at runtime. This work proposes an approach for runtime errors...
Measurement of air flows is an important task in many process monitoring systems. In applications like control of ventilation and air conditioning systems, robustness, ease of use, and cost are important issues calling for simple and effective sensor design. This paper investigates the use of commercial-off-the-shelf printed circuit board technologies for the fabrication of calorimetric flow sensors...
Power management and charging of batteries for wireless sensors become a problem when using them in the field applications. In this paper, we present RF energy harvesting circuit with three different approaches: resonator, number of multiplier stages and low pass filter (LPF). Resonator provide 30 times improvement in amplitude of input (100 mV) AC signal. In proposed circuit L type network, between...
Digital near-threshold logic circuits have recently been proposed for applications in the ultra-low power end of the design spectrum, where the performance is of secondary importance. However, the characteristics of MOS transistors operating in the near-threshold region are very different from those in the strong-inversion region. This paper first derives the logical effort and parasitic delay values...
CMOS integrated circuits are prone to hazards such as Single Event Transients (SETs) caused by radiation strikes in high energy radiation environments. For synthesis of high frequency signals for circuits used in such environments, we propose use of quadrature phase LC oscillators. In addition to providing higher tolerance to SETs, these oscillators are also able to provide wider tuning range, which...
Soft errors caused by particle strikes are expected to increase as technology scales down. This is partially because more single-event transients (SET) are latched by memory elements at the primary output of combinational circuits. To speed up the assessment of SET-induced soft errors, we propose a systematic analysis method to examine the probability of a SET eventually being latched. In previous...
As the process variation is dominating to cause the clock timing variation among chips to be much large, it is widely accepted that post-silicon tunable (PST) clock buffers can effectively resolve the the clock timing violation. Since PST buffers, which can reset the clock delay to flip-flops after the chip is manufactured, imposes a non-trivial implementation area and control circuitry, it is very...
Moderate overdrive of the supply voltage rather reduces total powers at high temperatures, which enables GHz design overcoming thermal runaway. We have examined the way in which reliability issues such as negative bias temperature instability (NBTI) and hot carrier injection (HCI) affect the product performance. 1) The high temperature and voltage acceleration test on 45nm products has revealed that...
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