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We report a new nano-switching ESD protection mechanism and dual-polarity Cu/SixOyNz/W nano crossbar array ESD structures. Experiments show full ESD protection featuring fast response of 100pS ultra low leakage of <2pA and ESD protection of >9A. New dispersed local ESD tunneling model and CMOS integration are reported.
We show that room temperature bonding of a 332 × 268 bump array can be realized by using ultrasonic bonding of cone-shaped bump. 25 μm-pitch area array of cone-shaped Au bump was fabricated on a Si wafer by using a photolithography and electroplating. A conventional planar electrode made of electroplated Au was used as the counter electrode. Ultrasonic bonding was carried out at room temperature in...
Multi-core scalar CPU are approaching processing rates of 256 GFLOPS. Transport latency and bandwidth (BW) between DRAM and processor are a substantial bottleneck to optimal system performance. This is, in large part, because board level, data transport occurs over legacy L-C transmission lines having limited BW over a limited distance. Consequently, high performance, systems running memory intensive...
In this paper, a lumped/discrete port de-embedding method by port connection error-cancelling network is proposed for full-wave modeling interconnect and packaging components with bump/pin array interfaces in 3D integration as well as conventional packaging systems. This method is based on the S-parameter matrix operation. Three calibration structures are simulated for extraction of the error-cancelling...
To improve the performance of MEMS device, it is critical that the effect of environmental parameters on these devices be controlled or eliminated. In this paper, we first developed a novel technique by employing thermal actuator and actuators array to rectify the micro deformation of MEMS substrate due to thermal mechanical stress as a result of temperature variation. This PTAA consisting of a 50...
Microsystems-enabled photovoltaic (MEPV) technology is a promising approach to lower the cost of solar energy to competitive levels. This paper describes current development efforts to leverage existing silicon integrated circuit (IC) failure analysis (FA) techniques to study MEPV devices. Various FA techniques such as light emission microscopy and laser-based fault localization were used to identify...
A novel method to fabricate the top electrode of ZnO nanogenerator is introduced in the article. Hydrothermal synthesis is adopted to grow ZnO nanowires array structure. And the sputtering process is employed as a simple fabrication method to form the top electrode. Scanning electron microscope (SEM) analysis has been carried out to identify different layers in nanogenerator. The energy harvesting...
This study proposed the use of combined nano-sphere lithography (NSL) and photo-assisted electrochemical etching (PAECE) to generate arrayed nano-pillar with high aspect ratio on silicon wafer, and then used for the application of photonic crystals (PCs) Sensor. The experiment result indicates the NSL can conveniently define nano-array and PAECE technique can effectively yield nano-pores and nano-pillars...
Silicon reflection-type arrayed waveguide gratings (AWGs) with −20dB crosstalk are experimentally demonstrated for the first time to our knowledge. The AWG has 14 output channels with 400GHz channel spacing and a footprint of 230×530 µm2. The minimum on-chip loss of 3.0 dB is achieved by using a second-order distributed Bragg reflector (DBR) facet.
We report the Si wire AWG without systematic phase error generated at the curved waveguides. A 200GHz spacing 16 channel devices were fabricated by ArF immersion and EB lithography and the results are compared.
A four-wavelength Si/III-V hybrid laser array was developed for energy-efficient silicon photonics CWDM transmitter. Under 4-ch simultaneous operation, stable lasing oscillations at four neighboring ring-resonator peaks are obtained with high output powers of >+5dBm/ch.
A hybrid silicon DFB laser array emitting over 200nm was integrated with EAMs (3dB bandwidth>30GHz). Four bandgaps spread over >100nm were realized using quantum well intermixing for increased spectral gain and for laser-modulator detuning.
The 20-way set associative 2.5MB slice ported L3 cache for the multi-core Xeon® Processor uses 0.108 um2 cell in a 22nm tri-gate technology with 2.7TB maximum bandwidth. It is protected by double-error correction/triple-error detection ECC. The basic building block is designed to support floorplan style on each processor with large L3 cache. On die fuse storage enables high resolution repair coverage...
We report a novel plasmonics silicon solar cell design, with the possibility of lower cost and higher efficiency. The proposed solar cells consist of radial p-n junction silicon nanopillars array in combination with plasmonics metal nanoparticles on its surface. Simple and solution processible methods such as metal assisted electroless chemical etching (MACE) and Spin on Dopant (SOD) techniques were...
In this paper, we successfully developed a fuel-self-propelled reaction device without consuming any external source of energy for passive micro direct methanol fuel cell (μDMFC) anodes by using the physical phenomenon of surface tension through three-type micro fluidic structures. Firstly, to prevent the backflow of fuel from the reaction zone due to generated gas pressure, highly dense micro-channels...
This paper reports on a micro force plate array for measurement of ground reaction forces of insect legs during running. The micro force plate is composed of a plate base and three beams whose surface and sidewall area are doped, which enable to detect both pressure and shear force. The device size and force resolution are 2000 μm × 500 μm × 20 μm (length × width × height) and 1 μN, respectively....
In this work, we perform optical simulation and investigate the effect of the periodicity (P) and diameter (D) of SiNW arrays (SiNWs) on light harvesting in thin-film silicon/PEDOT:PSS hybrid solar cells. The hybrid cell structure comprises 2 μιη thick silicon thin film with SiNWs textured surface and 50 nm thick PEDOT:PSS top layer. It is found that the light harvesting in the SiNWs is greatly enhanced...
We propose a highly sensitive pressure sensor using an elastic micro pyramid array with a gold-coated surface pressing on a resistive silicon beam. When a pressure was applied on the pyramid array, the deformation of each pyramid induced the larger contact area between each pyramid and the resistor. Since the pyramid array was coated by a gold layer, which had much lower resistivity than that of the...
MEMS liquid chromatography (LC) microchip with low dispersion and a low pressure drop turn structure was fabricated. In the turn structure, we used higher density pillar array at the inner side while lower density pillar array was used at the outer side to control inner and outer speed of a sample flow. An LC chip with an improved turn structure can obtain similar theoretical plate number (1233) compared...
We report field emission from nanometer-sharp tips of polarized PbZr0.2Ti0.8O3 (PZT) and silicon. The ferroelectric PZT emitters are a high-density array of single-crystal silicon tips that are coated with a 30 nm thick film of crystalline PZT in a batch fabrication process. The PZT emitter tips begin to emit electrons at fields as low as 2 V/μm and reach threshold emission at fields as low as 3.9...
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