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A∗ algorithm is an effective algorithm of path planning. In order to speed up the algorithm and reduce the search space, the OPEN table is adopted the fragmentation of hybrid data structure of binary heap and index array. At the same time the coefficient of risk rating is increased, the simulation body can judge straight or bypass the dangerous objects according to the environment, so as not to attack...
The 3D integration of Cellular Nonlinear Network architectures offers possibilities to increase the pixel and processor count remarkably by allowing integration of different processor functionalities to different chip layers. On the other hand, to avoid extensive use of Through Silicon Vias for inter and intracellular communication, it is important to be able to fit to each layer of silicon as complete...
According to the deficiency of Chord algorithm supporting single keyword query only, a P2P framework-Z_mirror by combining the Z_mirror and Chord is proposed for managing service resources, which supports DHT-based multi-keyword query and approximate query by means of Z_mirror index to improve resources searching ability. Experiments show that Z_mirrorChord has better efficiency and scalability for...
Si/mesa-etched Si p-n junction was fabricated by the reactive ion etching and the surface activated bonding. The SEM observation of their cross section indicated that the height of the mesa was approximately 13 μm. Their capacitance-voltage and current-voltage characteristics were also measured.
Due to the extreme complexity of neuroscience and neurosurgery, there is naturally a need for probing systems with more functions which can probe in three dimensions. For instance, nerves can size differently in different locations and can present three dimensional neuro imaging with multiple recording and stimulating points, calling for the new developments in this emerging field. It is also highly...
SRAM with backup circuits using a crystalline oxide semiconductor (OS) (e.g., a c-axis aligned crystalline oxide semiconductor (CAAC-OS) typified by CAAC In-Ga-Zn oxide (CAAC-IGZO)) is reported. Results of cell-level simulation based on 45-nm Si/100-nm OS process technology show backup time of 3.9 ns, recovery time of 2.0 ns, and break-even time of 21.7 ns. The OS-SRAM cell can replace a standard-SRAM...
Toppling during clean process is a general structure issue when we scale down critical dimension (CD)/increase aspect ratio (AR) and density of the nano structures. In this paper, we demonstrated a novel process with CH4 PLAD (plasma doping) conformal process to eliminate the toppling issue. A uniform C deposition layer from CH4 PLAD process wrapped the whole structure on the top/bottom/sidewall and...
Beam steering has been traditionally achieved by mechanical means. Even though these mechanical techniques have evolved over the past few decades, non-mechanical approaches, due to benefits such as increased speed, lower costs and reduced complexity, have gained considerable interest. In this work, we propose a non-mechanical beam steering of terahertz radiation method using a transient, or dynamic...
A semi-analytic approach for the electromagnetic analysis of large numbers of Through silicon vias (TSV) is presented in this paper. The method is based on cylindrical mode expansion method. The scattering and multi reflection effects between the vertical cylindrical vias are considered by expanding the electromagnetic waves surrounding the vias by cylindrical waves. As the method fully captured the...
A novel TSV structure, formed by two semi-cylinders combining with a quadrangular is proposed and analyzed in this paper. This novel structure can enhance the density of TSV array without significantly decreasing transmission performance and reducing impedance mismatch in TSV-RDL transmission line or depressing the signal crosstalk. Effects of design parameters, such as the side length of quadrangular...
Triangular barrier has been proposed and implemented for the first time in a punch-through diode based selector by dopant profile engineering. Vertical 4F2 diodes have been fabricated on an epitaxial Si stack consists of n+ / i / delta-doped p+ / i / n+ (NIPIN) layers by low temperature (sub-520°C) Si epitaxy. We experimentally demonstrate that while conventional NPN selectors exhibit severe sub-threshold...
As electronic product becomes smaller and lighter with an increasing number of function↚ the demand for high density and high integration becomes stronger.! Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration;!...
This paper presents an analytical model to describe the in-plane thermomechanical stresses of a unit TSV model. The goal is to use this model to evaluate the influence of key design parameters in TSV interposers prior to rigorous investigations. The key parameters considered herein are via pitch and array size. This analytical model is based on a circular unit TSV structure, the size of which (in...
A novel approach to embedded electronics cooling with a multi-phase microfluidic heat sink termed the Piranha Pin-Fin (PPF) is presented. Several first-generation PPF devices, as well as plain-channel and solid pin-fin heat sinks, have been fabricated and experimentally tested under single-phase adiabatic conditions. Details of the PPF device geometry and microfabrication process are provided. Plots...
Shared cache in multicore processors is an important hardware resource that should be utilized effectively to achieve high performance for parallel applications. It is critical to coordinate accesses by multiple threads to data that reside in shared cache to reduce cache contentions, and to improve cache hit rates of both shared and private data of threads. Poorly scheduled threads with regards to...
We are reporting the design of a new hypersonic filter with the operating frequency of ∼ 2–7 GHz, by means of a 2D nanophononic crystal (NPnC) platform. The 2D NPnC is composed of a periodic array of infinitely long nanorods of silicon, arranged in a square lattice of constant a0=96 nm, in air background. The radii of the CMOS compatible Silicon nanorods are r0=40 nm. Mechanical waves propagating...
To realize an over 10-Tbit/s bandwidth optical interconnection, a 1000-channel light source was demonstrated by using novel spot-size converters with a SiOx slab layer for a wide fabrication margin and by optimization done in consideration of the thermal interference between each channel in an LD array and also between the LD array chips for low power consumption. We expect the multi-channel and high-density...
A small autonomous device integrating MEMS, CMOS and photovoltaic (PV) cells has many attractive applications. For such a device, using light as a power source is preferable because power feeding and control signal transmitting can be done at the same time and in a remote manner. We demonstrated the remote power feeding to a MEMS actuator by light using PV cell array. In this article, we first proposed...
On October 16, 2012 five active radiation detectors employing the Timepix version of the technology developed by the CERN-based Medipix2 Collaboration were deployed on-board the International Space Station (ISS) using simple USB interfaces to the existing ISS laptops for power, control and readout. These devices successfully demonstrated the capabilities of this technology by providing reliable dose...
3D-IC technology discussed in this paper is based on vertical stacking of dies connected by through-silicon-vias (TSV). Vertical stacking helps reducing the wirelength but TSVs occupy space on device layers and their actual positions, arrangement, and physical properties determine the total wirelength. They also introduce thermo-mechanical stress that alters properties of devices that are close to...
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