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New method to extract the amount of floating (FG) charge (QFG) apart from oxide trapped charge (Qox) generated by program and erase (P/E) cycles is proposed, for the first time. QFG shift by P/E cycling shows asymmetry between programmed and erased states as follows; QFG exhibits the peak at ~100 cycles in programmed state, while QFG monotonically reduces in erased state. Next, the midgap voltage...
In this study, special STT-RAM were designed, built and tested, allowing to read and write at similar voltages. This is achieved by maximizing the Spin-Transfer-Torque (STT) efficiency on the storage layer magnetization during write and minimizing it during read. In order to achieve this STT tuning, double barrier magnetic tunnel junctions were prepared wherein the storage layer is sandwiched between...
In this paper, an embedded 2T SONOS nonvolatile memory structure has been proposed for an embedded NVM cell in 90nm standard HVCMOS process. This nonvolatile cell can be fabricated by several steps such as ONO formation, cell junction implant, removal ONO films, those steps are non-critical processes and masks. The cell is operated by CHEI programming and BTBT-HHI erasing. The cell has been confirmed...
We present a simulation methodology to analyze single bit fails in SRAMs with no visual defect to account for the failure. Our approach generates the MOS IV curves for all six transistors of the failing bit cell and uses this data to simulate read, write and read-disturb failures. A good agreement with the tester data then establishes the basis for the failure even in the absence of any visual defect(s)
This paper describes the comprehensive analysis on the performance of NAND flash/storage-class memory (SCM) hybrid solid-state drive (SSD) during write/erase (W/E) cycling for various applications. Since bit-error rate (BER) increases by cycling, increasingly stronger ECC should be applied, which results in longer ECC calculation time. Both program/erase latencies of the NAND flash memory and ECC...
3D AlOδ/Ta2O5−x/TaOy RRAM structure with three vertical cells is demonstrated. The devices maintain good performance in endurance (>108 cycles) and retention (>104s @85°C) in comparison with planar devices. The cells in different layers also exhibits excellent uniformity in SET/RESET voltages, HRS and LRS distributions. To further increase data storage density, large HRS/LRS resistance window...
This paper describes a byte alterable EEPROM with B4-HE (Back-Bias assisted Band-to-Band tunneling Hot-Electron injection) architecture employing three-transistor of AND-type unit cell for disturb-free operation. B4-EEPROM cell array has been fabricated using a 90nm flash process, and single-pulse program and erasure cycling has been confirmed up to one million, with keeping programming time of 10us...
This paper provides detailed characterizations of physical sources behind Flash memory based Physical Unclonable Functions (FPUFs). Universal process variations in Flash physical systems are identified and decomposed into layout, intrinsic, stress and bit-wise fluctuation sources. The study shows the understanding of systematic variations and noise sources are essential for improving the security...
For the first time, 4Mb split-gate type embedded flash is developed in 45-nm technology with 1M cycling endurance for mass production of various applications. Process integration is designed for logic compatibility, minimizing shift of logic device characteristics so that existing IPs can be used. By process optimization of triple-gate flash architecture, high speed operation (write time of 25us and...
Aiming for future nonvolatile memory applications the fabrication and electrical characterization of 3-dimensional trench capacitors based on ferroelectric HfO2 is reported. It will be shown that the ferroelectric properties of Al-doped HfO2 ultrathin films are preserved when integrated into 3-dimensional geometries. The Al:HfO2 thin films were deposited by ALD and electrical data were collected on...
Highly reliable solid-state drives (SSDs) with triple-level-cell (TLC) NAND flash and Advanced Error-Prediction Low-Density Parity-Check (AEP-LDPC) are proposed. To increase NAND flash's capacity, bits/cell have been doubled and tripled, which causes reliability to drastically degrade due to narrower VTH margins. Previously proposed Error-Prediction LDPC (EP-LDPC) error-correcting code (ECC) improved...
Solid-State Drives (SSDs) have impacted the computing platform and storage industry by providing substantially higher bandwidth random and sequential read write performance compared to Hard Disk Drives (HDDs). Due to these storage performance benefits, SSDs have also demanded more and stressed the NAND components beyond the typical usage models of removable storage media. In this work, several key...
Emerging Memories (EMs) could benefit from Error Correcting Codes (ECCs) able to correct a few errors in just a few nanoseconds; for example to cope with failure mechanisms that could arise in new storage physics. Fast ECCs are also desired for eXecuted-in-Place (XiP) and DRAM applications. This paper shows the key elements to implement a BCH code able to correct 2 errors in a page of 256 data bits...
SRAM with backup circuits using a crystalline oxide semiconductor (OS) (e.g., a c-axis aligned crystalline oxide semiconductor (CAAC-OS) typified by CAAC In-Ga-Zn oxide (CAAC-IGZO)) is reported. Results of cell-level simulation based on 45-nm Si/100-nm OS process technology show backup time of 3.9 ns, recovery time of 2.0 ns, and break-even time of 21.7 ns. The OS-SRAM cell can replace a standard-SRAM...
We propose for the first time a systematic evaluation of the performance and underlying trade-off of the use of ternary Hf1−xAlxOy oxides for RRAM application. We show that intermixing HfO2 and Al2O3 deposition cycles in a standard ALD process not only prevents crystallization of active layer but also significantly improve intrinsic retention and disturb-immunity properties at the expense of a small...
A new all-solid-state-drive (all-SSD) storage system, which does not suffer performance degradation due to garbage collection, for high-performance enterprise storage is proposed. The storage system has two new functions, namely, an indication of garbage collection (“GC indication”) and a dynamic allocation of a reserved SSD (“DLS allocation”). Cooperation between these two functions can dramatically...
We review recent results and discuss challenges and prospects of nonvolatile magnetic random access memory (MRAM). In particular, we will focus on recent developments in magnetoelectric memory (MeRAM), where electric field control is used to replace existing current-controlled write mechanisms to achieve lower power dissipation and higher density. We will discuss scaling trends and prototype crossbar...
A capacitor-less DRAM cell based on ferroelectric-gate memory transistor structure, FErroelectric-DRAM (FEDRAM), is introduced. Compared to the conventional DRAM cell, it offers much simpler cell structure, longer retention time, better scalability, and lower power consumption. Cell size of 4F2 can be realized. It is also most suitable for embedded applications. Recent developments of the HfO2-based...
Fully planar NAND Flash arrays operate with very low coupling ratio (CR), and the CR reduces even further when scaling below 20 nm half-pitch. As a consequence, they suffer from programming saturation due to excessive leakage through the intergate dielectic (IGD) if no special precautions (such as the use of high-k IGD or hybrid floating gate) are taken. In this work, we investigate the dependence...
We demonstrate the integration of multi-layer Inter-Gate Dielectrics (IGD) together with a thin Hybrid Floating Gate (HFG), in aggressively scaled planar NAND cells. The results show that excellent memory performance is obtained in short gate length transistors, with good retention and endurance. Simulations indicate that such gate stacks can drive the planar NAND Flash scaling down to 10 nm node.
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