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A three-dimensional length-extension mode (3D-LEM) resonator has been developed for fundamental physics purpose showing a very good frequency stability potential highlighted by a Quality factor Frequency product (Q.F) above 1013. Those characteristics are quite interesting for time & frequency applications but since a 3D structure is difficult to integrate, a planar two-dimensional (2D) resonator...
In this paper, thermal characteristics (Joule heating) induced by currents in short metal interconnect lines are studied. Electrical-thermal 3D-Finite Element Method (FEM) simulation is employed to model the property of temperature in short length metal lines and an empirical yet practical current model with metal line length effect is introduced. Consequently, the Irms current gain up to 25% in short...
In this paper, a Micro-Infrared Photo-elasticity (MIPE) system was set up and applied to evaluate the residual stress of Si chip around TSV. The MIPE system can only give overall stress information along thickness. To investigate the stress distribution around TSV quantitatively, finite element method was employed and the simulation results were compared with that of experimental measurements. Through...
The power system in package (SIP) includes multiple chips such as power IGBT, diodes and IC controllers. With more chips encapsulated in one single package, the silicon die crack failure is becoming more and more challenging. In this paper, a leadframe based power SIP package is investigated. The warpage induced reliability in assembly process is studied. The initial leadframe pad warpage will induce...
Through-silicon via (TSV) technology has been the core of the next generation of 3D integration. Although some TSV reliability issues have been addressed in some literatures, but the sidewall scallop resulted from Bosch etch process has not been thoroughly investigated. In this paper, we focus on the effects of different sidewall scallops on the interfacial stress evolution. An axi-symmetric single...
The effects the thickness of epoxy resin on the stress intensity factors (SIFs) of the edge-cracked adhesive joints subjected to external loads are investigated in the current paper. The three-layered joints composed of Silicon, epoxy resin and FR-4.5 are widely seen in the package solutions of CSP/FBGA for electronic devices. Cracks or delaminations from resin-substrate interface or resin-silicon...
Since 3D-TSV technology has been more and more popular aiming at the demand of lightweight and multi-functions of electronic devices in recent years, the μ-C4 bumps with smaller size which interconnect the stacked die will suffer more serious operating stress, and even one of the thousands bumps fails, the device will fail. Hence, it is meaningful to study the reliability of smaller size and higher...
Wafer transferring process is often used in the semiconductor packaging equipment. Wafer transferring system is an essential part in the IC equipment. Smooth and efficiency are the design requirement of wafer transferring. As the rising of smart phones and tablet PCs, thin wafer is increasingly demanding. Large and thin wafer is susceptible to damage because of gravity during transmission, which greatly...
In this paper, influences of the initial stress on the surface micromachining silicon nitride pressure sensor was analyzed and discussed. The residual stress in the diaphragm is a major issue that makes significant difference on the performance of surface micro machined pressure sensors, such as warpage, micro-cracking, delamination, debonding, and nonuniform stress profile of the membrane. The pressure...
In this paper, thermo-mechanical reliability of a three-dimensional (3D) package based on through-silicon-via (TSV) under different thermal cycling was investigated with finite element method. A finite element simulation of this 3D package was performed in order to compare the thermal stress and fatigue lives of the solder joints with and without underfill. It was found that the fatigue live of solder...
Advanced packaging is a key “More than Moore” (MtM) enabling technology [1]. In all of these advanced packaging processes the semiconductor die are becoming much thinner (e.g. 25–50 μm thick) and many packages include multiply stacked silicon die. This leads to very thin packages where there is a trade-off between the thickness of constituent package layers and their rigidity, thus leading to reliability...
Calculating leakage reactance of transformers is a very important factor in designing transformers. In the traditional two-winding transformer, the calculation methods of leakage reactance have been presented using the inductance deduced by the geometry mean length between two windings. However, it is difficult to calculate the leakage reactance in multi-winding transformers, because its structure...
Insulated gate bipolar transistors are the power semiconductors used for high current applications as a switching device. It is widely used in electrical and hybrid vehicles. It has become increasingly important to understand the reliability of these modules. The lifetime prediction is based on the assumption that the solder interconnections are the weakest part of the module assembly and that the...
We are reporting the design of a new hypersonic filter with the operating frequency of ∼ 2–7 GHz, by means of a 2D nanophononic crystal (NPnC) platform. The 2D NPnC is composed of a periodic array of infinitely long nanorods of silicon, arranged in a square lattice of constant a0=96 nm, in air background. The radii of the CMOS compatible Silicon nanorods are r0=40 nm. Mechanical waves propagating...
The industry keeps driving further miniaturization of electronic packaging for portable and handheld products, and wafer level chip scaling package (WLCSP) has high potential to fulfill these requirements. Larger chip can accommodate more functions. However, fatigue failure of WLCSP solder joint caused by material coefficient of thermal expansion (CTE) mismatch is getting worse due to chip size increase...
The stresses of TSV (Through Silicon Via) and Si chips in 3D-SiP were discussed with a large scale simulator based on FEM (Finite Element Method), ADVENTURECluster. In this study, the stacked layer structure of Si chips is modeled accurately. Thermal stress simulation for TSV structure in Si chips is carried out under thermal loads due to device operation and reflow process. In case of device operation,...
This paper aims to examine the feasibility of a novel resonant pressure sensor, which is realized by introducing a double-ended tuning fork (DETF) quartz resonator into a silicon substrate. Theoretical model and finite element simulation results are given to provide support for the scheme. Sensor prototypes are fabricated based on micromachining technologies. Experimental setup for testing is established...
The paper presents a piezoresistive absolute micro-pressure sensor for altimetry. This investigation includes the design, fabrication and testing of the sensor. An improved structure is studied through incorporating sensitive beams into the bossed-diaphragm structure. By analyzing the stress distribution of sensitive elements using finite element method (FEM), the configuration shows an enhanced sensitivity...
This communication describes numerical and experimental characterization of CMUTs for ultrasound transmission. Simulations based on finite elements method to model CMUTs electromechanical behaviour and to determine the dimensions of elementary cells are presented. In particular we analyze the collapse voltage variations for different parameters of a circular cell and the capacitance variations for...
Lifetime estimation of power semiconductors for various applications has gained technical importance. The main failures in high power semiconductors are caused by thermo-mechanical fatigue, mainly in solder and wirebonds, due to different coefficients of thermal expansions of the various packaging materials. Most of the lifetime models do not take all the operating parameters into account. There is...
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