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Advanced mobile computing devices nowadays demand for ever-increasing functionality, performance and bandwidth. The complexity of functional integration in mobile device has made it more challenging for wire bond and C4 bump flip chip packaging to meet the requirement of high I/O count and high density integration. Moreover, the extreme low-k (ELK) dielectric materials in the back-end-of-line (BEOL)...
Silicon interposer and bridge is a multi-chip 3D technology that enables high density die-to-die interconnect on a package substrate. It opens a new era for heterogeneous on-package system integration. This paper presents an overview of this packaging architecture and its capabilities from concept to results. The overall components are introduced and discussed including constituent building blocks,...
Using newly developed silicon micromachining technology that enables low-loss and highly integrated packaging solutions, we are developing vertically stacked transmitters and receivers at terahertz frequencies that can be used for communication and other terahertz systems. Although there are multiple ways to address the problem of interconnect and packaging solutions at these frequencies, such as...
The downscaling in VLSI systems and the use of new materials influences the reliability of components in terms of radiation more and more. The unavoidable presence of particle radiation on ground and in space leads to unwanted failures in the electronic devices. Concerning packaging materials, design and technology a lot of steps were done to avoid radiation sensitivity. Nowadays microelectronic for...
Wide band gap devices (e.g. Silicon Carbide, Gallium Nitride, etc.) provide significant opportunities for the power electronics industry. Compared to silicon, they have faster switching frequencies, better heat dissipation, and can operate at higher temperatures. But, WBG devices pose several challenges in terms of their packaging. This paper details the need for a co-design and simulation approach...
Smart ICT (Information and Communication Technology) such as “Big Data”, “Cloud computing” and Smart Functionalities such as Stand-alone Self-activating MEMS/Sensors construct Smart Systems which enable IoT (Internet of Things), IoE (Internet of Everything) thus Smart Society. To realize above-mentioned Smart Technologies, high-density, low-power consumption, wide-bandwidth, fast-operation semiconductor...
Advanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry...
Reducing switch loss and increasing heat-sinking capability were very important research topic in the high power density inverter for EV/HEV applications. In this paper, an inverter with a new development power module was built. The power module was packed using a hybrid SIC power device to reduce the switching loss and direct cooling technology to decrease the thermal resistance. The double pulse...
Packaging of 2.5D/3D applications is disrupting the high-density advanced package (HDAP) segment as silicon and packaging processes converge to deliver fan-out wafer level (FOWLP) and interposer based solutions. Silicon foundries are now in the package supply chain and driving methodology changes that impact manufacturing data formats, and how that data is accepted and verified.
The authors present a 3-chip mixed integration approach that combines monolithic silicon multi-terminal power chips and flip-chip assembly on a printed circuit board (PCB) for the realization of a multiphase power converter. The overall approach allows for taking advantage of the degrees of freedom offered by silicon and PCB technologies with a limited and well-mastered complexity. The multiphase...
High-current, large-area single SiC JBS diodes rated at 650V-200A and 1200V-100A were fabricated on a 150mm platform that demonstrate a low VF of 1.5V. The diodes exhibit a specific differential resistance, Rdiff, sp, of 0.74 and 1.65 mΩ-cm2, respectively. The devices were tested with similarly rated Si-IGBTs and the reduction in switching losses and QRR evaluated. The high-current diodes have also...
This paper discussed how to reduce cross talk and SSO noise to improve signal integrity for 3D PKG-VERTICAL CONNECTION UNIT. Due to the demand of high level IC integration, 3D packaging technology with multi-dies/chips in one package get rapid development. Traditional wire-bond multi-die stack package type have been unable to meet the challenge. TSV process seems to be an ideal solution, but with...
Semiconductor companies have developed 2.5D IC integration technology, which applies a silicon interposer with Cu through silicon vias (Cu TSVs) as a platform for interconnecting and integrating heterogeneous chips horizontally and vertically as a transition approach to 3D IC. The existing Cu TSVs might make the silicon interposers more fragile, due to structural non-homogeneity and weak interface...
When it comes to reducing form-factor and increasing functional integration of mobile devices, Wafer Level Packaging (WLP) is an attractive packaging solution with many advantages in comparison to standard Ball Grid Array (BGA) packages. With the advancement of various fan-out WLP (FOWLP), it is a more optimal and promising solution compared to fan-in WLP because it can offer greater flexibility in...
There is no doubt that component embedding technology becomes more visible in handheld applications like smart phones and wearables. Embedding technology is pushing the miniaturization which is a must for the next big wave of Wearable Electronics and Internet of Things (IoT). The technology is going to System in Package and the question today is how far you can go in miniaturization and how much of...
Silver sintering is a potential die attach technology to replace the solder technology for power electronic systems. A design of experiments (DoE) is performed in order to investigate the influences of sinter parameters as sinter pressure, temperature, duration, drying temperature and the interactions of these parameters on the shear strength of the Ag-sinter connection. Four sinter pastes have been...
We investigated why the blocking voltages of a power device are lowered during a durability test through a device simulation called Technology Computer Aided Design (TCAD) and measurements using the optical beam induced current (OBIC) method. We found that the spread of the depletion layer caused by the bonding wire is what decreased the blocking voltage.
The design to cost is a major challenge for the practices of power modules' development especially when faced with very polymorphic demands. The technologies used are not always appropriate in view of the required technical specifications, or can be too expensive, or too basic. Developing a power module consists in making the best technological choices to fit the mission profile of an application;...
As known to all, photometric and colorimetric quality of LED illumination mainly depends on LED chip, phosphor and sealant. The investigation on failure mechanism of the three parts carries critical meanings for improving reliability of LED production. This paper mainly focus on reliability and failure mechanism of the three kinds of phosphor and three kinds of sealant which are wildly used in high...
Flip chip package has matured significantly over the past several years, shifting from conventional eutectic Sn-Pb solder bump to Pb-free interconnection. It has become the preferred package solution for high performance IC and microprocessor device. From the last decade, there has been a significant focus on the development of Cu pillar bump interconnection in flip chip package which could meet current...
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