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Advanced heterogeneous integration (HI) technology is much needed for applications from edge to cloud to meet the stringent system-level requirements on performance, power, profile, cycle-time and cost (P3C2). In addition to 3DIC with TSV innovative packaging technologies such as silicon interposer (2.5D) and fan-out wafer-level-packaging (2D/3D) become new paradigm for the semiconductor industry...
Integrated fan-out wafer-level packaging (InFO-WLP) technology with state-of-the-art inductors (quality factor of 42 and self-resonance frequency of 16 GHz) has been demonstrated for heterogeneous integration of digital and radio frequency (RF) systems. InFO-WLP promises superior form factor, pin count, and thermal performance to existing flip-chip ball grid array (FC-BGA) packages. In addition, InFO-WLP's...
This paper is a study of the electromigration (EM) effects of micro bumps at silicon-silicon interface in 3DIC package for 28nm technology and beyond. Two joint schemes were designed and fabricated: one of the schemes was the joining of Sn-capped Cu post to ENEPIG (Electroless-Nickel-Electroless-Palladium-Immersion-Gold) UBM (Under-Bump-Metallurgy) pad on silicon substrate; the other scheme was the...
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