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Energy constrained systems become the cornerstone of emerging energy harvested or battery-limited applications in Internet of Thing (IoT) platforms. A promising approach is to operate at near threshold voltage ranges, which can significantly reduce energy per operation. However, due to increased sensitivity to variations and reduced noise margin at low voltages, resiliency becomes a major challenge...
Power Capping techniques are used to restrict power consumption of computer systems to a thermally safe limit. Current many-core systems employ dynamic voltage and frequency scaling (DVFS), power gating (PG) and scheduling methods as actuators for power capping. These knobs arc oriented towards power actuation, while the need for performance and energy savings are increasing in the dark silicon era...
Due to scaling of MOSFET, in this paper we have considered a triple material cylindrical gate all around(TM-CGAA) to study the SCEs and DIBL. An analytical threshold voltage model has also been reported. Center potential based modeling is carried out instead of surface potential for better accuracy.
Dependence of threshold voltage (VTH) of a device and its extraction techniques are studied in this paper. To exactly model the transition characteristics of device, value of VTH plays an important role. Accuracy in the assessment of VTH of a device also depends upon the extraction method utilized. Several estimation techniques are already reported in literature. However, these techniques fail to...
The structure of a conventional laterally diffused MOSFET (LDMOSFET) build on InGaAs is modified by placing trenches in the epitaxial layer. The gate of the proposed device (LDMOSFET) is placed in a oxide (Al2O3) trench between the source of the structure for creating twice channels in the p-base. Parallel conduction of twice channels leads to increase in drain current, higher transconductance, lower...
This paper explores the analog/RF performance of cylindrical surrounding double gate (CSDG) MOSFET in comparison to Cylindrical surrounding Gate (CSG) MOSFET for future nano CMOS devices. CSDG MOSFET has more gates on the silicon substrate to control the channel than any contemporary device. This device has one more cylindrical gate than the CSG MOSFET. That extra gate controls the inner core of the...
Electrical characteristics of three-dimensional Zinc Oxide nanowire field effect transistor has been studied using 3-D TCAD tool. The device exhibited a good output performance that clearly shows linear and saturation mode with threshold voltage of 0.75V, field-effect mobility of ∼108 cm2/v.s and on/off current ratio of ∼109. This device is then introduced with defect and interface charge density...
This paper presents the development of a 1 MHz enhancement mode GaN (eGaN) FET based 4-switch buck-boost converter with bootstrap driver for automotive applications. Conventionally, with Si MOSFETs, it is difficult to optimize the efficiency of a 4-switch buck-boost converter since the high side switches need to switch at high frequency or completely conduct the output/input current in either buck...
In this paper, we propose a vertical super-junction strained-Si channel power MOSFET to improve the breakdown voltage, drain current, threshold voltage, and transconductance. In the proposed structure, a P-pillar forming super-junction with N-drift region is incorporated to get higher blocking voltage due to reduction in electric field inside the drift region. In order to lower the on-resistance,...
Although cryptography constitutes a considerable part of the overall security architecture for several use cases in embedded systems, cryptographic devices are still vulnerable to the diversity types of side channel attacks. Improvement in performance of Strained Silicon MOSFETs utilizing conventional device scaling has become more complex, because of the amount of physical limitations associated...
In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The paper reports on the performance of novel n-on-p edgeless planar pixel sensors...
This paper investigates the switching rate and temperature dependence of parasitic (false) turn-on of power transistors when switched in power converters implemented in silicon IGBTs and Silicon Carbide (SiC) MOSFETs. It is shown that although high switching rates are normally desirable for minimizing the switching losses, this can result in shoot-through arm currents due to the combination of a Miller...
In this work, we investigate workfunction (WK) fluctuation of gate-all-around Si nanowire MOS devices by solving a sets of 2D Schrödinger-Poisson equations. We discuss characteristic fluctuation in view of randomly interactive quantum confinement with subbands and wavefunctions. The influences of metal-grain size and channel width on the random WK-induced characteristic fluctuation are studied; additionally,...
Resistive switching devices and neuromorphic computing systems, while an attractive solution to minimize compute bottlenecks, suffer from sneak-path problem and area inefficient implementations respectively. This has prompted research in developing beyond-CMOS functional blocks that can serve as a compact single device circuit block (selector and oscillator respectively). In this work, we explore...
Body bias effects on the laser-induced transient current peak, duration, collected charge and amplification factor are experimentally evaluated. The results are promising for radiation-hardened circuit design.
This paper presents the current-voltage (I–V) characteristics of the recently proposed Silicon-on-Ferroelectric Insulator Field Effect Transistor (SOFFET). In this work we have concentrated on Partially Depleted (PD) structure. PD-SOFFET is based on the silicon-on-insulator (SOI) device technology and utilizes a negative capacitance that can be achieved by inserting a layer of ferroelectric insulator...
In this paper, the effect of silicon body thickness (TSi) and silicon body width (WSi) variation on DC characteristics in 100 nm gate length silicon-on-insulator (SOI) junctionless (JL) and junction transistors has been investigated by using numerical simulations. The digital figure-of-merits characteristics such as threshold voltage (VTH), on-current, subthreshold voltage, and drain-induced-barrier-lowering...
Data with increasing bandwidth requires future general-purpose as well as application specific microprocessors to improve performance endlessly. Transistor scaling, novel transistor structures, novel state-of-art VLSI design techniques and new computer architectures are the key drivers for boosting power and performance of microprocessors. Unfortunately, the processor cooling technique is unable to...
A novel methodology for the post placement leakage reduction based on employment of the stress-enhanced filler (SEF) cells was developed. Desired reduction of sub-threshold leakage in test chip silicon was achieved by placement of SEF cells close to the most leaking devices. In the standard cell rows the “optimization zones”, representing portions of the row located between two consecutive fixed cells...
14 nm technology node bulk silicon FinFETs and SOI FinFETs and 14 nm SOI Ultra-Thin-Body and BOX nFETs were irradiated under bias using a 10 keV X-ray source. Irradiation resulted in significant changes in the threshold voltages of the SOI devices and large changes in the off-state current of the bulk FinFETs.
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