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A wide variety of existing and emerging applications in recognition, mining and synthesis and machine-to-human interactions tolerate small errors or deviations in their computational results. Digital systems can exploit this error tolerance to increase their energy efficiency, which is crucial in high performance wearable electronics and in emerging low power systems for the internet-of-things. A...
Many-core processors facilitate coarse-grained reliability by exploiting available cores for redundant multithreading. However, ensuring high reliability with reduced power consumption necessitates joint considerations of variations in vulnerability, performance and power properties of software as well as the underlying hardware. In this paper, we propose a power-efficient reliability management system...
Gaming on mobile platforms is highly power hungry and rapidly drains the limited-capacity battery. In multi-threaded gaming, each thread has different processing requirements and even a single slow thread may lead to Quality of Service (QoS) violations. Further, modern mobile platforms are equipped with asymmetric multi-core processors, so that different cores exhibit diverse power and performance...
An accelerator-rich architecture (ARA) is composed of heterogeneous accelerators with an on-chip memory system. Compared to the general-purpose processors, an accelerator demands short and predictable latency to its local on-chip memory to satisfy its performance target. Moreover, an accelerator requires a much higher off-chip memory bandwidth than a CPU since it consumes much more data in a given...
Energy-efficiency continues to limit peak computational performance in digital systems. To drive continued energy-improvements, designers of modern digital systems are relying on multiple, smaller voltage domains for enhanced voltage-scaling. Switched-capacitor (SC) voltage converters are a promising alternative to traditional switched-inductor regulators due to their suitability for efficient, fully-integrated...
Recently, Electric Vehicles (EVs) have been considered as new paradigm of transportation in order to solve environmental concerns, e.g. air pollution. However, EVs pose new challenges regarding their Battery LifeTime (BLT), energy consumption, and energy costs related to battery charging. The EV power consumption may be estimated by having the route information and the EV specifications. Also, by...
Sternocleidomastoid (SCM) is a paired muscle that stretches along both sides of the neck area. It acts as an accessory muscle of inhalation. Abnormal SCM contraction during asthma is usually a sign of further respiratory impairment. Thus, monitoring SCM muscles has great significance in asthma assessment and control. In this work, we develop a wearable monitoring system based on an optical sensor...
With the fast development of the GPU server technology, cloud gaming has become popular in recent years. Unlike the traditional desktop gaming where the graphic rendering is performed locally using the user's personal graphics card, cloud gaming runs multiple games to support many users at the same time in the data center where most of the rendering jobs are done in the remote GPU cluster. The rendered...
Aside from the benefits it brings, 3D-IC technology inevitably exacerbates the difficulty of power delivery with volumetrically increasing power consumption. Recent work managed to “recycle” current within the 3D stack by linking the different layers' supply/ground nets into a series connection. This charge-recycled (also known as voltage-stacked, or V-S) scheme provides a scalable solution for 3D-IC's...
As research on improving energy efficiency becomes prevalent, the necessity of a tool to accurately estimate power is increasing. Among various tools proposed, McPAT has gained some popularity due to its easy-to-use analytical power models. However, McPAT's prediction has several limitations. Although under- or over-estimated power from unmodeled and mis-modeled parts offset each other, it still incorporates...
Power delivery is a well-known challenge for high-end microprocessor systems. Comparatively, mobile computing platforms typically consume order-of-magnitude lower currents, but economic and volume constraints limit the quality of the Power Delivery Network. In addition, the trend towards GHz+ operating frequencies and the ubiquity of low-power techniques such as clock-gating and power-gating, make...
Spin-Torque-Transfer RAM (STTRAM) is a promising technology for high density on-chip cache due to low standby power and high speed. However, the process variation of magnetic tunnel junction (MTJ) and access transistor poses serious challenge to sensing. Nondestructive sensing suffers from reference resistance variation whereas destructive sensing suffers from failures due to unoptimized selection...
We present a novel technique for optimizing the read operation of spin-transfer torque (STT) MRAMs by employing a correlated material in conjunction with a magnetic tunnel junction (MTJ). The design of the proposed memory cell is based on exploiting the orders-of-magnitude difference in the resistance of the two phases of the correlated material (CM) and triggering operation-driven phase transitions...
Aggressive technology scaling exacerbates the problem of voltage emergencies in emerging MPSoC systems. Network-on-Chips, the de-facto standard for connecting on-chip components in forthcoming devices play a central role in providing robust and reliable communication. In this work, we propose DrNoC (droop resilient network-on-chip)-two microarchitectural techniques to mitigate voltage emergency-induced...
Low-power embedded processing typically relies on dynamic voltage-frequency scaling (DVFS) in order to optimize energy usage (and therefore, battery life). However, low voltage operation exacerbates the incidence of soft errors. Similarly, higher voltage operation (to meet real-time deadlines) is constrained by hard-failure rate limits. In this paper, we examine a class of embedded system applications...
A global reference-circuit (RC), which means one RC is shared with many sensing circuits (SC), is being considered for high-bandwidth STT-RAMs because of the low power consumption and small area characteristic. However, using the global RC for high-bandwidth STT-RAMs causes a droop effect and coupling noise effect, leading to the significant performance degradation. Thus, the validity of using the...
Security and low power have emerged to become two essential requirements to modern design. In this paper, we have proposed a new hardware security primitive: digital bidirectional function (DBF) designed on FPGA to meet both criteria. The DBF has two forms of functions and implements two mappings of opposite directions. The DBF can be easily implemented using hierarchical lookup-table (LUT) structures...
The Intel Xeon E5 v3 family is the latest generation of enterprise-grade, high-performance, Xeon microprocessors. It implements several new power-management technologies and features aimed at improving power/performance efficiency, increasing performance, and improving power delivery. It is the first commercial x86 processor to manage voltage/frequency optimizations on a per-core granularity. This...
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