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In our previous studies [1], [2], good power supply wirings on a chip have provided excellent high-speed switching and tinny power swing fluctuation. In this study, we again confirmed this by higher precision re-measurements correlated with simulations. If the power integrity (PI) would be better on the circuit, the circuit would be expected that the CMOS driver makes it sure to take higher-speed...
Interventional radiologists and staff members, during all their professional activities, are frequently exposed to protracted low doses of ionizing radiation. The authors present a novel approach to perform on line monitoring of the staff during interventional procedures by using a device based on a CMOS Active Pixel Sensor (APS). The sensor performance as an X-ray radiation detector has been evaluated...
Test structures comprehending several combinations of FET detector sizes and bow-tie antennas were designed and fabricated in a 0.13 µm standard CMOS technology. Measurement results from these structures provide a quantitative comparison basis for the design of a future real-time high-frame rate THz camera, providing an insight on the optimization of the FET size.
A fully-digital VCO-based ADC featuring a novel beat frequency detection scheme is demonstrated in 65nm LP CMOS. The proposed beat frequency based ADC is unique compared to previous VCO-based ADCs in that it is highly effective in measuring extremely small changes (e.g., 0.01%) in the VCO frequency within a short sampling time (e.g., 100 VCO periods). Direct amplifier-less A-to-D conversion of a 1...
A 10GS/s 6b time-interleaved ADC in 65nm CMOS is presented in this paper. A partially-active flash sub-ADC structure is proposed to improve the ADC power efficiency and a source-follower based boot-strap T&H circuit is proposed to reduce input kickback and improve the ADC bandwidth. The four-phase 2.5GHz clocks for the sub-ADCs are derived from a 5GHz Nyquist frequency input clock. This leads...
A four-channel time-interleaved pipelined ADC employs a new timing calibration technique to suppress mismatch-induced spurs and achieve a Nyquist-rate SNDR of 44.4 dB. Designed in 65-nm CMOS technology, the ADC draws 120 mW, providing an FOM of 219 fJ per conversion step.
A single-chip three-dimensional(3-D)Hall sensor for high-accuracy three-axis magnetic-field measurements is presented. The chip contains a 3-D Hall device, the analog signal conditioning circuit, an A/D converter and the digital signal-processing unit. The 3-D Hall device contains horizontal and vertical Hall elements. The horizontal Hall element measures the perpendicular component, and four vertical...
We present top-illumination type 100% Ge-on-Si photodetector, which achieved high-performance level ready for various optical network applications. We also present a Ge waveguide photodetector operating over 50Gb/s with high responsivity.
This work presents CMOS on-chip antennas for wireless chip-to-chip communication. In order to provide for high antenna efficiency, the antennas have been manufactured on an ultra-thin substrate with a thickness of 17.5 µm. The antennas are manufactured in the top metallization layer and are used as ground supply for the CMOS circuitry, thus requiring no dedicated chip area. Prototypes of the proposed...
This paper presents a CMOS photo amplifier for real-time living body detection. The photo amplifier consists of a high sensitivity photo-detector and a transimpedance amplifier realized in a standard 0.18 µm CMOS technology. The transimpedance amplifier has 100dbO transimpedance and 20MHz bandwidth and the detector was capable of outputting400 mVpp for 50-Ω loads. The designed photo amplifier has...
This paper presents an integrated UWB short-range impulse radar implemented in a 130 nm CMOS process. The transmitter can digitally generate various waveforms with up to 10 GHz bandwidth at 5 dBm peak power. The receiver utilizes a time interleaved scheme to support a 20 GS/s effective sampling rate. Sample-domain averaging of multiple identical received waveforms reduces the required digitization...
The goal of this work is the improvement of an existing design-oriented model of the 5-contact vertical Hall-effect sensor integrated in CMOS technology. Such a model should facilitate the work of designers, permitting them to simulate the sensor, the biasing and processing electronics together with the same electrical simulator. In this paper, focus is put on two physical effects that alter the electrical...
An ultra-wideband (UWB) low noise amplifier (LNA) was designed and fabricated using 0.18μm 1.8V CMOS technology. The adoption of forward body biases (FBB) in a 3-stage distributed amplifier enables an aggressive scaling of the supply voltages and gate input voltage to 0.6V. The low voltage feature from FBB leads to more than 50% power consumption saving to 4.2mW. The measured power gain (S21) is higher...
This paper presents a k-band (18–26.5 GHz) high gain low noise amplifier (LNA) in 65-nm CMOS mixed signal process. The LNA has a peak gain of 20.46 dB at 22.45 GHz and a −3 dB bandwidth of 3.8 GHz. S11 of the chip is better than −11 dB and S22 better than −15 dB across the band. The measured smallest noise figure (NF) is 3.4 dB. The whole chip consumes 11mA current under 1.1V supply voltage and occupies...
We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating...
This paper gives an overview of our research work on Oxide Resistive switching memory (OxRAM) at technology and design level. The OxRAM technology has been developed in order to be co-integrated with low-voltage advanced CMOS technologies. The device electrical characteristics show: (i) a switching time of 100ns at 1V, (ii) an excellent data retention at 150°C and (iii) a high endurance up to 108...
Current, voltage and time (frequency) are the base parameters describing an electronic system. In the 1700's, Benjamin Franklin was one of the first experimenting with current tests, followed by many others shaping the current domain. In 1963 Frank Wanlass (Fairchild Semiconductor) planted the first seeds of using current testing as part of a structural approach to validate integrated circuits when...
This paper presents signal integrity characterization of 3D TSVs and interconnect using high-speed I/O in a 3D chip-package system. The authors designed and fabricated a Gunning Transceiver Logic (GTL) I/O Test IC using Tezzaron 3D CMOS 150um technology. The test IC has two different tiers which are labeled top and bottom. GTL I/O is placed on each tier to evaluate the TSV and interconnect signal...
This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset errors of comparators that occur during high speed operation. Utilizing the proposed calibration, comparators are designed with near-minimum size transistors and built-in reference levels. The ADC achieves an SNDR of 30.9dB at Nyquist and consumes...
This paper presents the design and experimental results of a high speed, low-power, thermometer coded and current steered 6-bit digital-to-analog converter (DAC). It is based on a hybrid architecture with a switched current matrix controlled by the four most significant digital bits, and a conventional 2-bit current source controlled by the two least significant bits. The DAC occupies 0.15 mm2 chip...
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