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In the last decade Quantum dot Cellular Automata technology has been one of the most studied among the emerging technologies. The magnetic implementation, NanoMagnet Logic (NML), is particularly interesting as an alternative solutions to CMOS technology. The main advantages of NML circuits resides in the possibility to mix logic and memory in the same device, the expected low power consumption and...
This paper investigates the improvement margins in term of energy efficiency of analog filters. Starting from a landscape of analog filters presented at ISSCC until 2012, energy limits for most common analog filters architectures (Gm-C and Active-RC) are traced. Active-RC filters with reduced bandwidth requirements have larger margins of improvements compared to Gm-C. Technology scaling impact is...
This paper presents the high frequency characterization of a fabricated in-plane nano-electro-mechanical resonator in which the doubly clamped nano-wire acts as a suspended channel for a dual gate junction-less field-effect-transistor that is used for the resonance frequency detection. The applied DC biases to gates of the transistor were optimized to amplify the detected output signal of the resonator...
A CAM-based (Content Addressable Memory) system for fast Watermarking extraction has been proposed and implemented on hardware system using FPGA device. The system has a simple structure, does not employ any Central Processor Units (CPUs) or complicated algorithms for extracting hidden information. The authors take advantages of CAM which has an ability of parallel multi-match mode for designing the...
The aim purpose of this study is to evaluate the ESD protection using BIMOS transistor in the RF and fast swing application for advanced CMOS technology in 32 nm high k metal gate & bulk substrate. The ESD target is 1kV HBM and the RF one is 100 GHz broadband. Moreover the DC behavior is also performed. Thus, the challenge here is to be efficient in ESD protection with a minimum of parasitic capacitance...
An I2C programmable 0.35µm CMOS System-on-Chip (SoC) for bi-dimensional gas-sensor arrays providing extended dynamic range read-out with suitable embedded A/D converter and digitally controlled row temperature has been developed. The SoC also features low-power consumption, low-cost production, wide re-configurability and thus large scale compliance with several types of micro-sensors, achieving maximum...
The gate disturb degradation mechanism in silicon-oxide-nitride-oxide-semiconductor (SONOS) FETs with a highprecision threshold voltage (Vth) tuning function, which is designed to compensate for the Vth mismatch in order to achieve high-performance analog circuits, was investigated in detail. A tendency for an unintended positive Vth shift under typical bias conditions in analog circuits was identified...
To achieve higher voltage analog and power devices, the deep trench isolation breakdown voltage must withstand the higher operating voltages. Optimization of deep trench etch to produce a straighter etch profile enable a void free poly filled trench, adding HF clean improve liner oxide film quality and changing liner oxidation process change the fill profile enable the oxide liner thickness to increase...
A flow is presented to evaluate analog CMOS circuit performance pending temporal MOSFET degradation. The change in threshold voltage due to the bias temperature instability (BTI) mechanism is used as a paradigm. The tasks of performance evaluation and MOSFET degradation are decoupled in the flow. This is extended to severalize the model of degradation at three time scales: that of signal processing,...
This paper discusses, for the first time, how the statistical SRAM design analyses should be changed when: (1) the time-dependent (TD) voltage margin variations (MV) after the screening test will dominate the overall behavior of the MV variations and (2) the shapes of the MV distribution will change from the Gaussian to the complex mixtures of Gamma distributions. We discuss on the SRAM TD-MV analyses...
Advanced SoC designs regularly use Dynamic Voltage and Frequency Scaling (DVFS) to achieve high performance and low power targets of portable systems. In this paper, we focus on optimization of a Voltage Sense Amplifier (VSA) in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FD-SOI) technology to achieve high performance operations over the Ultra Wide Voltage Range (UWVR) from 1.3V to 0.4V...
The dependences of the effective channel length on the gate voltage for MOSFETs with halo are extracted, and their average behaviors are studied. It is found that they provide the important information about not only the channel structure, but also the effects of the gate voltage and the substrate voltage on the channel, which are helpful for both technology and design engineers to get the common...
In this paper, we investigate the impacts of single trap induced Random Telegraph Noise (RTN) on the drain current, stability of 6T SRAM cells and logic circuits of Si and Ge NanoWire (NW) FETs. The trap position dependence of the RTN amplitude (ΔIds/Ids) along the channel length direction is examined. For Si-NW FET, significant RTN impact is observed for trap located near the middle region of channel...
Accurate statistical compact model extraction and circuit simulation are key issues in contemporary SRAM design. The high statistical variability of the small SRAM cell transistors in combination with high cell density leads to yield problems determined by 5-6σ deviations from the mean. The compact modeling approach presented in this paper utilizes a firm understanding of the physical phenomenon underlying...
Based on shunt - series feedback topology, a 10dB broadband low noise amplifier is developed for tuner front end applications. With such gain, low noise operation with high linearity is a challenging specification. In this paper, it is shown that there is a direct relation between gain and minimum noise figure under input/output simultaneous matching condition. The measurement of a packaged device...
Microwave imaging based on UWB pulses can detect breast cancer, even at an initial stage. To favor the adoption of this method in screening campaigns, it is necessary to replace the expensive and bulky RF instrumentation used so far with ad-hoc designed circuits and systems. In this paper we report on a possible design solution that aims to integrate many of the components in CMOS integrated circuits...
A low power, small form factor, cyclic ADC is proposed. By replacing the MDAC with an open loop residual amplifier, it relaxes the gain bandwidth requirement of the operational amplifier to save power. The residual amplifier is background calibrated without extra replica to avoid performance mismatches, and also save area and power. Timing reschedule scheme is proposed for each conversion step to...
This paper gives an overview of our research work on Oxide Resistive switching memory (OxRAM) at technology and design level. The OxRAM technology has been developed in order to be co-integrated with low-voltage advanced CMOS technologies. The device electrical characteristics show: (i) a switching time of 100ns at 1V, (ii) an excellent data retention at 150°C and (iii) a high endurance up to 108...
There is a worldwide race to build a computer which exploits the counterintuitive principles of quantum mechanics1. Silicon is one of the most promising platforms for emerging quantum information technologies for two reasons: one, it possesses many of the key desirable criteria for low-error quantum information processing, and two, the microelectronics industry has decades of experience with producing...
The A-to-D converter here presented is part of a bigger system able to sense and monitor electrical/physical parameters in particles detectors, for LHC experiments.
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