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A 20 GS/s 6b time-interleaved ADC is implemented in 32 nm CMOS SOI with an embedded time-to-digital converter to sense timing skew, and the randomness of process mismatch is exploited to compensate for the clock misalignment and dynamic offset errors of comparators that occur during high-speed operation. To achieve low-power consumption at high-speed operation with small-size transistors, a low-complexity...
This paper describes a 5GS/s 6bit flash ADC fabricated in a 32nm CMOS SOI. The randomness of process mismatch is exploited to compensate for dynamic offset errors of comparators that occur during high speed operation. Utilizing the proposed calibration, comparators are designed with near-minimum size transistors and built-in reference levels. The ADC achieves an SNDR of 30.9dB at Nyquist and consumes...
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