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Significant peak power (PP), thus power droop (PD), during test is a serious concern for modern, complex ICs. In fact, the PD originated during the application of test vectors may produce a delay effect on the circuit under test signal transitions. This event may be erroneously recognized as presence of a delay fault, with consequent generation of an erroneous test fail, thus increasing yield loss...
The possibility of achieving test compaction by using multi-cycle tests led to the development of procedures that produce compact multi-cycle test sets for the detection of single stuck-at faults, for the detection of transition faults, and for n-detections of single stuck-at faults [1]-[4]. The advantages of compact diagnostic test sets motivated the development of the test compaction procedures...
Functional operations of a Static Random Access Memory (SRAM) are strongly affected by random variability in core-cell transistors and by the variability-induced threshold voltage mismatch between the transistors of the Input-Output (IO) circuitry (especially Sense Amplifiers). This variability also affects the faulty behavior of the SRAM array. This paper is focused on the analysis of static and...
Sensor data fusion is a common approach to provide accurate and fault-tolerant sensor readouts in a multi-sensor system. This paper proposes an efficient data fusion algorithm using convex optimization for a multi-sensor system with given post-calibration statistical characteristics. A preprocessing step called screening is proposed to quickly detect multiple faulty sensors and exclude them from the...
The coming era of chips consisting of billions of gates foreshadows processors containing thousands of unreliable cores. In this context, high energy efficiency will be available, under the constraint that applications leverage the large amount of computing cores, while masking frequent faults of the chip. In this paper, an high-level method is proposed to map and manage a parallel application on...
In nanoscale era, Negative Bias Temperature Instability (NBTI) and Positive Bias Temperature Instability (PBTI) weaken PMOS and NMOS transistors, respectively, leading to performance degradation. This paper presents a comprehensive analysis of NBTI and PBTI impacts on SRAM decoders including single stage static and dynamic as well as two stage static decoders while applying realistic addressing schemes...
Typical SOC designs use processors and therefore, trust in such processor cores is essential. The 2011 Embedded Systems Challenge (ESC 2011) [1] showed a wide range of possibilities to attack a processor through hardware Trojans. We propose an approach to detect suspicious behavior of a processor and thus assess if the processor is trustworthy or not. A countermeasure, called Processor Protection...
Integrated circuits suffer from severe variation effects with technology scaling, making their timing behavior increasingly unpre-dictable. Timing speculation is a promising technique to tackle this problem with the help of online timing error detection and correction mechanisms. In this paper, we propose to use redundancy addition and removal (RAR) technique to optimize timing-speculated circuits...
This work proposes a generic methodology for selecting meaningful subsets of indirect measurements (signatures). This allows precise predictions of the DUT performances and/or precise pass/fail classification of the DUT, while minimizing the number of necessary measurements. Two simple figures of merit are provided for ranking sets of signatures a priori, before training any machine learning model...
Testing M-S circuits is a difficult task demanding high amount of resources. To overcome these drawbacks, indirect testing methods have been adopted as an efficient solution to perform specification based tests using easy to measure metrics. In this work, a testing technique using octrees in the measure space is presented. Octrees have been used in computer graphics with successful results for rendering,...
Nowadays Graphical Processing Units (GPUs) have become increasingly popular due to their high computational power and low prices. This makes them particularly suitable for high-performance computing applications, like data elaboration and financial computation. In these fields, high efficient test methodologies are mandatory. One of the most effective ways to detect and localize hardware faults in...
The major bottleneck for technology scaling is the growing rate of hardware failures. Process variations are becoming extreme and sensitivity to radiation is becoming severe. In addition, intrinsic failures such as device parameter degradation are accelerating the wear-out. All of these are leading to higher random in-filed failures and shorter device lifetime. The 2011 ITRS (International Technology...
Efficient access to on-chip instrumentation is a key enabler for post-silicon validation, debug, bringup or diagnosis. Reconfigurable scan networks, as proposed by e.g. the IEEE Std. P1687, emerge as an effective and affordable means to cope with the increasing complexity of on-chip infrastructure. To access an element in a reconfigurable scan network, a scan-in bit sequence must be generated according...
Scan chain diagnosis has become a critical issue to yield loss in modern technology. In this paper; we present a scan chain partitioning algorithm and a scan chain reordering algorithm to improve scan chain fault diagnosis resolution. In our scan chain partition algorithm, we take into consideration not only logic dependency but also the controllability between scan flip flops. After partition step,...
Manufactured devices have a diverse perfor-mance/quality profile due to process variations. Devices with superior performance and quality are of higher value while the rest can be sold for a lower price. Separating manufactured devices according to their performance is defined as quality/performance binning and is a very effective way of lowering average device cost. In this manner, devices that have...
The emergence of many-core platforms increases the need for high memory bandwidth, which in turn creates the need for vast amounts of on-chip memory space. Designers must carefully provision the on-chip memory resources to meet application needs. Efficient memory management is extremely critical since it has a great impact on the system's power consumption and throughput. While memory hierarchies...
Graphic Processing Units are very prone to be corrupted by neutrons. Experimental results show that in the majority of the cases a typical application like matrix multiplication is affected by multiple output errors. In this paper we evaluate how different thread distributions impact the multiple output errors occurrence. The reported results and the performed architecture analysis give practical...
Fault injection is fundamental to evaluate the dependability of embedded software. Analyzing the interaction between the software and hardware components when hardware faults occur is efficient, but it is only possible once physical prototypes are available. On the other hand, fault injection on Hardware Description Language (HDL) models is a common practice that can significantly improve the verification...
Three-dimensional stacking technology promises to solve the interconnect bottleneck problem by using Through-Silicon-Vias (TSVs) to vertically connect circuit layers. However, manufacturing steps may lead to partly broken or incompletely filled TSVs that may degrade the performance and reduce the useful lifetime of a 3D IC. Due to combinations of physical factors such as switching activity, supply...
This paper describes a new programmable low power test compression method that allows shaping the test power envelope in a fully predictable, accurate, and flexible fashion by adapting the existing logic BIST infrastructure. The proposed hybrid scheme efficiently combines test compression with logic BIST, where both techniques can work synergistically to deliver high quality test. Experimental results...
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