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This paper presents a multilevel spin-orbit torque magnetic random access memory (SOT-MRAM). The conventional SOT-MRAMs enables a reliable and energy efficient write operation. However, these cells require two access transistors per cell, hence the efficiency of the SOT-MRAMs can be questioned in high-density memory application. To deal with this obstacle, we propose a multilevel cell which stores...
Physically Unclonable Functions (PUFs) are emerging cryptographic primitives used to implement low-cost device authentication and secure secret key generation. While several solutions exist for classical CMOS devices, novel proposals have been recently presented which exploit emerging technologies like magnetic memories. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) is a promising...
This paper presents the design and modeling of a strained magneto-tunnel-junction (S-MTJ) for stochastic computing. Due to the inherent half-way deterministic switching offered by an S-MTJ when operated with voltage generated strain, a true random number generator can be implemented due to the random thermal noise that acts on the free layer at room temperature. Using a compact model for the S-MTJ,...
Shannon's seminal work on Boolean operators — AND, OR, NOT has been the backbone of on-chip digital logic design. This set of the so called basic gates excludes an important mathematical logical operator — the Material Implication (IMP) logic (and its complement (NIMP)), shown in Fig. 1(a). IMP gate along with a NOT/XOR/NIMP gate forms a complete logic basis. Moreover, including IMP as a basic gate...
Spin Transfer Torque Magnetic Random Access Memories (STT-MRAM) are based on Magnetic Tunnel Junctions (MTJs) made out of two ferromagnetic electrodes separated by a MgO tunnel barrier.
In this paper, we propose a non-volatile stochastic computing (SC) scheme using voltage-controlled magnetic tunnel junction (VC-MTJ) and negative differential resistance (NDR). The proposed design includes a VC-MTJ based true stochastic bit stream generator and VC-MTJ and NDR based stochastic adder, multiplier, register, which are experimentally demonstrated using 60nm VC-MTJ and CMOS NDR connected...
Spin-based memory devices are gaining importancedue to multiple advantages like, zero standby power, high writeendurance and fast read, write operations. Besides storage, Spin Torque Transfer (STT)-based Magnetic Tunnel Junctions (MTJs) and Racetrack Memories (RMs) are also being investigated for logic applications, especially in the context of in-memory computing and neuromorphic architectures. Despite...
The rapid development of low power, high density, high performance SoCs has pushed the embedded memories to their limits and opened the field to the development of emerging memory technologies. The Spin-Transfer-Torque Magnetic Random Access Memory (STT-MRAM) has emerged as a promising choice for embedded memories due to its reduced read/write latency and high CMOS integration capability. Inner properties...
Spin-transfer torque random access memory (STT-RAM) is considered as a promising candidate to replace SRAM as the next generation cache memory since it has better scalability and lower leakage power. Recently, 2-bit multi-level cell (MLC) STT-RAM has been proposed to further increase data density. However, a key drawback for MLC STT-RAM is that the magnetization directions of its hard and soft domains...
Spin-Transfer Torque Random Access Memory (STT-RAM) has been identified as an advantageous candidate for on-chip memory technology due to its high density and ultra low leakage power. Recent research progress in Magnetic Tunneling Junction (MTJ) devices has developed Multi-Level Cell (MLC) STT-RAM to further enhance cell density. To correct the write disturbance in MLC strategy, data stored in the...
Density is one of the major design factors of magnetic random access memory (MRAM). Very recently, a tri-level cell (TLC) structure was proposed to enhance the storage density of MRAM. In this work, we propose a new self-reference sensing scheme for the TLC MRAM cell based on its unique property called state ordering. Simulation results show that compared to conventional design, our proposed self-reference...
In this study, special STT-RAM were designed, built and tested, allowing to read and write at similar voltages. This is achieved by maximizing the Spin-Transfer-Torque (STT) efficiency on the storage layer magnetization during write and minimizing it during read. In order to achieve this STT tuning, double barrier magnetic tunnel junctions were prepared wherein the storage layer is sandwiched between...
This paper describes an original concept of thermally assisted MRAM in which memory and logic functions are combined in the same stack. The memory cell is represented by a magnetic tunnel junction having an exchange biased storage layer and a soft reference layer (called sense layer), replacing the conventional pinned reference layer. The write of the storage layer is ensured by a combination of heating...
Spin-transfer torque random access memory (STT-RAM) has widely believed as a promising candidate for the post-silicon nonvolatile memory technology. In many recent researches, STT-RAM has demonstrated many attractive characteristics, such as nanosecond access time, high integration density, adjustable non-volatility, and good CMOS process compatibility. As the distinction between the two boundary...
Magnetic Tunnel Junction (MTJ) devices are CMOS compatible with high stability, high reliability and non-volatility. A macro-model of MTJ with precessional switching is presented in this paper. This model is based on Spin-Transfer Torque (STT) writing approach. The current-induced magnetic switching and excitations was studied in structures comprising a perpendicularly magnetized polarizing layer...
An extremely practical simulation program with integrated circuits emphasis (SPICE) incorporating model parameters of magnetic tunnel junction (MTJ) was developed. The simulator provides reliable simulation results in spintronics circuit design because it can accurately calculate various MTJ characteristics that actual devices have, that considerably influence the operation margin and power dissipation...
Spin-transfer torque random access memory (STT-RAM) has recently gained increased attentions from circuit design and architecture societies. Although STT-RAM offers a good combination of small cell size, nanosecond access time and non-volatility for embedded memory applications, the reliability of STT-RAM is severely impacted by device variations and environmental disturbances. In this paper, we develop...
Magnetic Random Access Memory (MRAM) is an emerging technology with the potential to become the universal on-chip memory. Among the existing MRAM technologies, the Thermally Assisted Switching (TAS) MRAM technology offers several advantages compared to the others technologies: selectivity, single magnetic field and integration density. As any other types of memory, TAS-MRAMs are prone to defects,...
Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory technology aiming on-chip or embedded applications. In recent years, many researches have been conducted to improve the storage density and enhance the scalability of STT-RAM, such as reducing the write current and switching time of magnetic tunneling junction (MTJ) devices. In parallel with these efforts, the continuous...
It has been predicted that a processor's caches could occupy as much as 90% of chip area for technology nodes from the current. In this paper, we study the use of multi-level spin-transfer torque RAM (STT-RAM) cells in the design of processor caches. Compared to the traditional SRAM caches, a multi-level cell (MLC) STT-RAM cache design is denser, fast, and consumes less energy. However, a number of...
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