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Wireless power transmission using mid-range magnetic resonance has become an important technology in body area sensor systems. Recent researches have used fine-tuned impedance matching for wireless power transmission at fixed distance. However, this method is significantly sensitive to the distance change between two devices since the impedances at both ends must be perfectly matched. Hence, it is...
Implementing a variable fractional delay (VFD) filter in Farrow model is costly as each coefficient of a VFD filter is a polynomial rather than a numerical scalar as in a conventional digital filter. This paper presents a method for the design of VFD filters with sparse coefficients which admits efficient implementation. The design is accomplished in two phases with the first phase identifying locations...
In this paper, a readout circuit with a novel two-stage amplification method is presented for current sensing of 64-channel CNT(carbon nanotube) arrays. Key blocks of the proposed readout circuit consist of a transimpedance amplifier (TIA) block and an 11-bit SAR-ADC. In whole sensing sequence, the TIA block converts sensing currents of 64-channel CNT sensors into corresponding voltage levels through...
This paper presents a new minimax method called bi-minimax design for simultaneously suppressing the peak errors of variable frequency response (VFR) and peak errors of variable fractional-delay (VFD) of odd-order variable fractional-delay (VFD) filters. To achieve this goal, we minimize a compound error function that combines the two peak errors through a weighting factor. After linearizing the non-linear...
The problem of designing robust H∞ filters for Markovian jump systems with time-varying delays and parametric uncertainties is studied. Some delay-dependent conditions for the existence of the desired H∞ filter are obtained via a new mode-dependent Lyapunov functional such that the corresponding filtering error system is robustly stochastically stable with a prescribed H∞ performance level. The attractive...
In this paper, we present an efficient and high throughput hardware implementation of the RC4 algorithm. The main idea of the proposed architecture is the utilization of a tri-port RAM to reduce the memory resource and to increase throughput. The proposed design requires two clock cycles for generating one byte of ciphering key and uses only a block of 256 bytes RAM. These result in 50% increment...
This work presents a look-up table-based (LUT-based) algorithm for scanline-based rendering of OpenVG. The proposed method can deal with arbitrary number of scissoring rectangles. The rasterization and scissoring in the proposed architecture can be performed concurrently to reduce rendering time. The scanline-size buffers used as scissoring LUTs result in low area overhead. Moreover, a linked list...
In this paper, a novel genetic algorithm (GA) is presented to tackle with the constrained pinning control problem for complex networks. The information of the node degree is incorporated in the design so that a set of pinned nodes can be duly obtained. In addition, the control strength of each selected node is assigned by the use of a decrease-and-conquer approach, satisfying the total control strength...
An image compression algorithm suitable for focal plane integration and its hardware implementation are presented. In this approach an image is progressively decomposed into images of lower resolution. The low resolution images are then used as the predictors of the higher resolution images. The prediction residuals are entropy encoded and compressed. This compression approach can provide lossless...
Hand posture classification is popular in systems that require an effective human-machine interface. Previous classification algorithms suffer from inaccurate results when it is difficult to distinguish a hand from a wrist. To overcome this difficulty, this paper proposes a new algorithm for hand posture classification that uses a histogram of convex defects around the segment of a hand to be classified...
In retargeting of a nano-watt CMOS reference circuit, we adopt an advanced compact MOSFET model to describe the drain current consistently in strong and weak inversion levels. Based on this model, we describe all bias conditions in terms of ratios of the channel widths and lengths. Taking the effect of very long channels into account, we formulate the threshold voltage as a function of the drain-source...
This live demonstration presents a high fill factor 6 transistor per pixel CMOS image sensor (CIS) based on a single inverter that modulates light illumination to pulse width supporting ultra low supply voltage requirements. It has a compact readout circuitry for pulse-based signal processing without A/D converter at the output. A 64 × 64 pixel array was fabricated using 130 nm CMOS technology. The...
Range-Doppler Algorithm (RDA) and Chirp Scaling Algorithm (CSA) are two widely used Synthetic Aperture Radar (SAR) imaging schemes. Both require multiple transpose operations which increase the total processing time significantly. In this paper, we propose transpose-free flow for both RDA and CSA. This is achieved by modifying the existing flows in order to utilize the access patterns favored by the...
In this paper we present a correlation based error estimation technique using a residual test signal for the linearization of multibit feedback DACs of lowpass and bandpass Delta-Sigma analog-to-digital converters. Using residual test signal insertion allows operating in background with only limited loss in peak performance during test. Opposed to dynamic element matching techniques, which are limited...
A model-first flow is demonstrated for designing and validating a high-speed serial receiver in a digital TV. Starting with a functional model of the top-level mixed-signal system rather than with transistor-level designs helps detect problems due to the increasing interaction between the analog and digital circuits. Once the functionality of the system model is verified, the model can be leveraged...
This demonstration shows how an inexpensive high frame-rate USB camera is used to emulate existing and proposed activity-driven event-based vision sensors. A PS3-Eye camera which runs at a maximum of 125 frames/second with colour QVGA (320×240) resolution is used to emulate several event-based vision sensors, including a Dynamic Vision Sensor (DVS), a colour-change sensitive DVS (cDVS), and a hybrid...
This paper presents multi-channel DVB-T transmitter design based on the software and hardware co-design approach. Part of the transmitter which requires less computational complexity is implemented by the SW module while the other part which requires more computing to generate the OFDM signal waveform is processed by the HW module. The data stream processed by the SW module is transferred to the HW...
An overview of recent progress in terahertz monolithic integrated circuits (TMICs) is presented in this paper. Semiconductor technologies available for TMIC implementation are described, and recent results on amplifiers and signal sources operating at THz band are discussed. Finally, the current status of THz integrated transceiver system is reviewed.
This paper presents a recently developed dynamic stereo vision sensor system and its application for fall detection towards safety for elderly at home. The system consists of (1) two optical detector chips with 304×240 event-driven pixels which are only sensitive to relative light intensity changes, (2) an FPGA for interfacing the detectors, early data processing, and stereo matching for depth map...
The BCH codes are widely used as Error Correcting Code (ECC) schemes for NAND Flash Memories. There have been strong demands to implement NAND Flash controller having low cost, low power and high throughput. We focus on BCH implementation since it has the largest portion in the controller. In this paper, we configure the 3-stage pipelined BCH decoder: syndrome computation, Berlekamp-Massey algorithm...
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