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This paper presents a spin-orbit torque magnetic random access memory (SOT-MRAM) using perpendicular-anisotropy magnetic tunnel junction (p-MTJ). In spite of conventional p-MTJ based SOT-MRAMs which need an external magnetic field to achieve a deterministic switching, the proposed cell uses a spin-torque transfer (STT) current where we show that the cell needs only two access transistors. This can...
This paper presents a multilevel spin-orbit torque magnetic random access memory (SOT-MRAM). The conventional SOT-MRAMs enables a reliable and energy efficient write operation. However, these cells require two access transistors per cell, hence the efficiency of the SOT-MRAMs can be questioned in high-density memory application. To deal with this obstacle, we propose a multilevel cell which stores...
In this paper, a high-speed and low-power latched comparator in a 65-nm CMOS process is presented. In our proposed structure, a latched circuit with an adjusted delayed-clock with no static power consumption is added to the conventional latch-type comparator in order to enhance the clock frequency and reduce the power consumption and the delay time. Therefore, the maximum clock frequency of our proposed...
This paper presents a low-power instrumentational amplifier (IA) design for EEG signal acquisition for seizure detection. The proposed structure provides a power per channel of 0.92 µW at supply voltage of 0.8 V. Due to the use of buffer structures and impedance boosting loops in the proposed design, the input impedance has reached up to 160 GΩ and 16 GΩ at 1 Hz and 10 Hz frequencies, respectively...
Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future non-volatile memories. However, the write operation in 1T-1MTJ STT-RAM bit-cells is asymmetric and stochastic which leads to high energy consumption and long latency. In this paper, a new write assist technique is proposed to terminate the write operation immediately after switching takes place in...
This paper presents a novel subthreshold 8T-SRAM for ultra-low power applications. The proposed SRAM cell improves write margin by at least 22% to the standard 6T-SRAM cell at supply voltage of 1V compared. Furthermore, read static noise margin is improved by at least 2.2X compared to the standard 6T-SRAM cell. Although by the use of the proposed SRAM cell, the total leakage power is increased for...
In this paper, a novel 7T-SRAM cell for ultra-low power applications is proposed. The proposed SRAM cell is fully functional at subthreshold voltages down to VDDmin=200mV. In this technique, separate read/write bitlines and wordlines are used that makes read and write operation independent. The 7T-SRAM cell proposed in this paper, improves static read noise margin, write margin, and write time by...
In this paper, a multi-level wordline driver scheme is presented to improve 6T-SRAM read and write stability. The proposed wordline driver generates a shaped pulse during the read mode and a boosted wordline during the write mode. During read, the shaped pulse is tuned at nominal voltage for a short period of time, whereas for the remaining access time, the wordline voltage is reduced to save the...
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