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Power delivery design plays a critical role in ensuring power delivery integrity and achieving overall design power efficiency. A power delivery network (PDN) consists of a multiplicity of passive and active components, which interact with each other in a complex manner. Under this context, power delivery design is a multifaceted problem and a holistic system optimization involving joint design of...
In 3D-IC integration and its implied resource optimization, a particularly critical resource is deadspace — regions between floorplan blocks. Deadspace is required for through-silicon via (TSV) planning and other related design tasks, but the effective use of this limited and highly-contested resource requires effort. While most previous work focuses on a single design issue at a time, we propose...
The power distribution network of an integrated circuit must be checked throughout the design process to ensure that supply voltage fluctuations do not exceed certain critical thresholds. One way of doing this is by simulation, which requires knowledge of the circuit currents that load the grid. These currents are hard to specify. In many cases, and certainly during early power grid design, they may...
Voltage partitioning on functional units/blocks targeting peak power minimization has been demonstrated to be effective for energy reduction considering voltage island shutdown impact. However, the existing technique can only solve this NP-hard problem efficiently on small designs. In this paper, a much faster linear time approximation scheme is proposed, which can approximate the optimal voltage...
Power integrity has become increasingly important for the designs in 32nm or below. This paper discusses a silicon-validated methodology for microprocessor power delivery modeling and simulation. There have been many prior works focusing on power delivery analysis and optimization. However, none of them provided a comprehensive modeling methodology with postsilicon data to validate the use of the...
In the period of extreme CMOS scaling, reliability issues are becoming a critical problem. These problems include issues related to device reliability, in the form of bias temperature instability, hot carrier injection, time-dependent dielectric breakdown of gate oxides, as well as interconnect reliability concerns such as electromigration and TSV stress in 3D integrated circuits. This tutorial surveys...
The well-studied gate-sizing optimization is a major contributor to IC power-performance tradeoffs. Viable optimizers must accurately model circuit timing, satisfy a variety of constraints, scale to large circuits, and effectively utilize a large (but finite) number of possible gate configurations, including Vt and Lg. Within the research-oriented infrastructure used in the ISPD 2012 Gate Sizing Contest,...
Recent advances in semiconductor process technology especially interconnects using Through-Silicon Vias (TSVs) enable heterogeneous system integration where dies are implemented in dedicated, optimized process technologies and then stacked together to form a system. Compared to conventional wire-bond chip interconnections, TSVs offer several advantages such as high density, low latency, low power,...
Parametric yield estimation is one of the most critical-yet-challenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematic-level simulation) to efficiently estimate the performance...
Although modern analog placement algorithms aimed to minimize area and wirelength while satisfying symmetry, proximity, and other placement constraints, the generated layout does not reflect the circuit performance very well because of the routing-induced parasitics on the critical current/signal paths. This paper introduces the current-path constraints in analog placement, demonstrates their impact...
In Throughput Computing, the data can be processed independently with a substantial amount of threads running similar programs, referred to as kernels, or shaders for graphics specific workload. A Throughput Computing device, such as GPU, requires task latency tolerance to hold the context of the outstanding threads, and data latency tolerance to hold spaces for memory requests issued from the threads...
Process migration (PM) is a method used in Multi-Processor System on Chips (MPSoCs) to improve reliability, reduce thermal hotspots and balance loads. However, existing PM approaches are limited by coarse granularity (i.e. can only switch at application or operating systems boundaries), and thus respond slowly. Such slow response does not allow for fine control over temperature, nor does it allow...
In this paper a novel approach to discrete state space modeling of nonlinear analog circuits is presented, based on the introduction of an underlying discrete analog transition structure (DATS) and the related optimization problem of accurately representing a nonlinear analog circuit with a DATS. Starting from a circuit netlist, a partitioning of the state space to the discrete model is generated...
Leveraging machine learning has been proven as a promising avenue for addressing many practical circuit design and verification challenges. We demonstrate a novel active learning guided machine learning approach for characterizing circuit performance. When employed under the context of support vector machines, the proposed probabilistically weighted active learning approach is able to dramatically...
TPL-friendly detailed routers require a systematic approach to detect TPL conflicts. However, the complexity of conflict graph (CG) impedes directly detecting TPL conflicts in CG. This work proposes a token graph-embedded conflict graph (TECG) to facilitate the TPL conflict detection while maintaining high coloring-flexibility. We then develop a TPL aware detailed router (TRIAD) by applying TECG to...
This paper is intended to give a brief tutorial understanding of on-die power grid effects. Board, package and on-die power grids deliver power to a die having both global (full-die) as well as local (intra-die) transient effects. With a simple excitation model and a detailed die/package/board model, one can come to understand the dynamic effects occurring inside the die in terms of global and local...
Parallelizing power grid simulation with factorization-based direct or preconditioned iterative methods is a challenging task due to the data dependency among forward and back substitution. In this paper, we propose two approaches to parallelize forward and back substitution. The first approach exploits the parallelism by computing independent variables in parallel; the second approach resolves the...
A modern smartphone or tablet-PC is typically equipped a high-resolution and large-size display, which is a primary power consumer. In spite of the relatively high power efficiency of organic light emitting diode (OLED) displays, the integrated display subsystem exhibits low energy efficiency due to power losses in the battery and the boost voltage conversion. In this paper, we for-mulize the system...
A clock mesh network synthesis method is proposed which enables clock gating on the local sub-trees in order to reduce the clock power dissipation. Clock gating is performed with a register clustering strategy that considers both i) the similarity of switching activities between registers in a local area and ii) the timing slack on every local data path in the design. This is the first work known...
The modern integrated circuit (IC) manufacturing process has exposed chip designers to hardware Trojans which threaten circuits bound for critical applications. This paper details the implementation and analysis of a novel ring oscillator network technique for Trojan detection in an application specific integrated circuit (ASIC). The ring oscillator network serves as a power supply monitor by detecting...
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