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Renesas Mobile Corporation (RMC), established on the first of December 2010, comes to the global chipset market with advanced and innovative products and services for mobile phones, car infotainment solutions, consumer electronics and industrial applications. The modem group in RMC comes with a strong pedigree from Nokia. The group has developed all Nokia's in-house modems and formed an essential...
A 65nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signalling allows the FPGA to operate at voltages down to 370mV without any parameter tuning. We show both 2.6× total energy reduction and 6.4× performance improvement at the same...
This paper presents a design methodology for robust and low-energy clock networks for ultra-low voltage (ULV) circuits. We show that both clock slew and skew play important roles in achieving high maximum operating frequency (Fmax) and low clock energy in ULV circuits. In addition, clock networks in ULV circuits are highly sensitive to process variations. We propose a variation-aware methodology that...
A near-/sub-threshold programmable clock generator is proposed in this paper. The major challenge of the ultra-low voltage (ULV) circuits is that the lock-in range of the delay line is easily affected by the environmental variations. In the proposed clock generator, there is a PVT compensation unit which consists of a set of delay line and a PVT detector. The unit is responsible for adjusting the...
Determinant factors of the minimum operating voltage (VDDmin) of CMOS logic gates are investigated by measurements of logic-gate chains in 65nm CMOS. VDDmin consists of a systematic component (VDDmin(SYS)) and a random variation component (VDDmin(RAND)). VDDmin(SYS) is minimized, when the logic threshold voltage of logic gates equals to half supply voltage (VDD). The tuning of the logic threshold...
This paper presents a don't-care-based synthesis technique for reducing glitch power in FPGAs. First, an analysis of glitch power and don't-cares in a commercial FPGA is given, showing that glitch power comprises an average of 26.0% of total dynamic power. An algorithm for glitch reduction is then presented, which takes advantage of don't-cares in the circuit by setting their values based on the circuit's...
Excessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device. For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory. Effective and efficient test set postprocessing techniques based on X-identification and power-aware X-filling have been proposed for external and...
Minimizing the clock tree has been known as an effective approach to reduce power dissipation in modern circuit designs. However, most existing power-aware clock tree synthesis algorithms still focus on optimizing power in flip-flops, which might have limited power savings. In this work, we explore the pulsed-latch utilization in clock tree synthesis for further power savings. We are the first work...
Hardware-based physically unclonable functions (PUFs) leverage intrinsic process variation of modern integrated circuits to provide interesting security solutions but either induce high storage requirements or require significant resources of at least one involved party. We use device aging to realize two identical unclonable modules that cannot be matched with any third such module. Each device enables...
This article presents a study of the impact of packaging on the memory and power walls, in the context of application properties. The analysis is supported by characterizations of 130 hardware designs spanning 30 years, along with both microarchitectural simulation and actual-hardware performance counter measurements of 25 applications. It is shown that if trends in supply pin count (growing as the...
In this talk, key design considerations in deep-volt are summarized with emphasis on the difference between normal voltage design and ultra-low voltage design.
The challenges for ultra-low-voltage operation are reviewed from the device side. The degradations of transistor variability and subthreshold swing are the main obstacles for the ultra-low-voltage operation. A new transistor structure with fully-depleted channel is discussed as a possible solution.
A new three-dimensional (3D) integration technology based on a reconfigured wafer-to-wafer bonding method called a super-chip integration has been developed to achieve low-power and high-performance system-on-a chip (SoC). A number of known good dies (KGDs) are simultaneously aligned and bonded onto lower chips or wafers with high alignment accuracy by using a new self-assembly technique in a super-chip...
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