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In the past several years, CMOS image sensors (CISs) with sub-single-electron noise level, particularly, deep sub-electron read noise (less than 0.5e-rms), have been reported. Such an ultra-low noise level is realized with a reduced floating diffusion (FD) node capacitance for attaining the high pixel conversion gain (CG) [1,2], and a high-gain readout circuitry with noise-reduction capabilities [3,4]...
A 1-transistor SRAM on bulk substrate is presented. The device is fabricated in 28 nm foundry baseline process with an additional buried N-well (BNWL) implant. The unit cell consists of a lateral MOS for memory access operations and intrinsic vertical open-base bipolar structures for self-latch function. The bit cell operation and the disturb immunity are verified at high temperature. Using 28 nm...
We present a physically grounded modeling, simulation, and parameter-extraction framework that targets design and engineering of ultra-scaled devices and next-generation channel materials. The framework consists of a fast and accurate Schrödinger-Poisson solver/mobility extractor coupled to a device simulator. The framework brings physical modeling of semiconductor channels to device design and engineering...
Experimental results show that the measurement and interpretation of short-channel effects (SCE) are misleading in advanced SOI MOSFETs. Part of SCE is due to the parasitic contribution of the back gate via channel coupling. We demonstrate that the contributions of each gate to the overall SCE can be discriminated. Numerical simulations indicate that their mutual relevance depends on the transistor...
While the scaling of MOS transistors is still ongoing, the miniaturization of the DRAM storage capacitor is reaching a critical limit. A promising solution consists of eliminating the capacitor. Instead, the charges can be stored in the floating body of an SOI MOSFET, which is also used to read out the memory states. The floating-body 1T-DRAM takes advantage of floating-body and coupling effects that...
We have shown here a comprehensive set of results on the coupling factor in a UTBB technology based on TCAD simulation. An interesting result is the degree to which the coupling factor is not constant across the possible realistic range of biases, and that not only back-gate depletion may play a role, but fixed charges and work function variation change the behavior. This suggests that these dependencies...
We have investigated a mechanism for an abnormally large floating gate (FG) interference reported in 2y nm NAND flash device. Based on the experimental and simulation results, we have found that the root cause is attributed to a depletion of polysilicon (poly-Si) layer for the control gate (CG). It was also found that the poly-Si depletion gives deterioration in the program performance. This work...
The ballistic conductance of a device consisting of two quantum point contacts, separated by a distance smaller than the spin coherence length, has been measured at 4.2K. A conductance plateau at 0.5 (2e2/h) is observed in the absence of external magnetic field indicating spontaneous spin polarization. This happens when the confining potentials of the point contacts are made sufficiently asymmetric...
The alpha-subunit of the rapid delayed rectifier Ikr has been identified to be composed of multiple function domains. However, much less is known about the electrophysiological consequences of the interaction properties in the assembled channel protein. In this paper, we present a detailed conformational kinetic model through characterizing allosteric interactions between the voltage sensing domain...
The paper presents a detailed study on the idle leakage reduction techniques on partially depleted silicon-on-insulator (PD-SOI) CMOS SRAM. The most promising leakage reduction techniques that have been proposed are introduced, analyzed and compared into 65 nm low-power PD-SOI technology, taking into account all the SOI specific effect. Especially, it is shown that the leakage reduction techniques...
This paper explores new capabilities brought on by Independently Driven Double Gate CMOS transistors (IDGMOS) for analog baseband design. Since the gates are disconnected, the corresponding channels are coupled resulting in a dynamic threshold voltage tuning. This operation mode is exploited to create new analog functions and low-voltage circuits. A current mirror is redesigned using IDGMOS and it...
This paper presents an experimental characterization of floating-gate devices to be used as variable threshold transistors exploitable for trimming analog circuits. The presented data show that good accuracy can be achieved in circuit trimming, but also that the analog characteristics of floating-gate devices are inherently worse than those of standard transistors fabricated with the same technology.
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