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In this paper, a 1.1-$\mu \text{m}$ -pitch 33-Mpixel 240-fps backside-illuminated 3-D-stacked CMOS image sensor with three-stage cyclic-cyclic-successive-approximation-register (SAR) analog-to-digital converters (ADCs) is developed. The narrow-pitch interconnection technology that connects the pixels and arrayed ADCs inside the pixel area is described. The 3-D-stacked architecture, constructed using...
In the past several years, CMOS image sensors (CISs) with sub-single-electron noise level, particularly, deep sub-electron read noise (less than 0.5e-rms), have been reported. Such an ultra-low noise level is realized with a reduced floating diffusion (FD) node capacitance for attaining the high pixel conversion gain (CG) [1,2], and a high-gain readout circuitry with noise-reduction capabilities [3,4]...
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