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In this paper, the compensative structure assisted the convex and concave corner structures etch in inductively coupled plasma reactive ion etch (ICP-RIE) have been studied. In anisotropic silicon etching, under the Bosch patent, sequentially alternating etch and passivation cycles can easily achieve high aspect ratio silicon structures. But, the feature size of the convex and concave corner structures...
To meet CD specifications required for 10nm and beyond Fully-depleted SOI devices (FDSOI) techniques alternative to EUV lithography are being developed. This article reports on the demonstration of Self-Aligned Dual Patterning (SADP), multi-beam electronic lithography and Directed Self-Assembly (DSA) to fabricate silicon fins with width < 10nm and high-k / metal gates with 11nm CD, or to shrink...
This paper explores the formation process of surface pyramid morphologies and etching characteristics during the texturing process of silicon heterojunction (SHJ) solar cells. Our research discovered that pyramid size followed a linear correlation with etch amount at the transition point of planes {100} to {111} as the etch rate reached the transition point. Several techniques were developed to control...
In this study, the intrinsic hydrogenated amorphous silicon oxide (a-SiOx:H) thin films were prepared by Electron Cyclotron Resonance Chemical Vapor Deposition (ECR-CVD). High density plasma of ECR-CVD has many advantages: (1) faster deposition rate, (2) no electrode contamination, (3) low ion bombardment. The process parameters effect on a-SiOx:H thin films such as dilution ratio was investigated...
A technique which retains wafer-scale processing and packaging compatibility is described for customizing the dynamics of individual silicon resonators. The approach uses laser ablation of a protective conformal layer (parylene) to expose silicon in regions that are targeted for mass removal by subsequent DRIE. The technique is demonstrated on a planar axisymmetric resonator design whereby the frequency...
Millimeter- and submillimeter-wave imaging systems for astronomy, planetary, and Earth science applications are increasingly moving towards large focal plane arrays. The relatively long wavelengths together with focal ratios encountered imply mm-sized pixels, and when one considers arrays with a hundred to thousands of pixels, we have to deal with optical elements of quite substantial size. In many...
3D manufacturing at micron scale with very low roughness is a key enabling technology for the realization of micromechanical parts both for mechanical devices and for critical components such as printer head nozzles and high precision molds. The only currently available technique in the field of IC micro technology is nanolithography by two photon absorption [1]. We report the implementation of a...
Blistering of 11 nm and 45 nm-thick Al2O3 layers deposited by ALD on silicon substrates is studied in Al-Al2O3-Si structures fabricated using a field isolated process. Blisters are shown to be unevenly distributed and with different dimensions depending on the structure area. After chemical etching down to silicon, round voids are revealed underneath the blisters depending on the etchant used, indicating...
The aim of this work is to present the main technological developments carried out at FBK for micro machined radiation sensors used in High Energy Physics (HEP) experiments. We report on the main technological issues to integrate silicon etching (wet and dry) techniques in the fabrication flow for silicon detector and we show some examples of innovative detectors realized by means of these technologies
This paper reports an extension of a recently demonstrated technique to fabricate nano-electro-mechanical systems (NEMS) using sidewall transfer lithography (STL). The process uses three pattern transfer steps. Each step only requires optical lithography, making the method suitable for low-cost, wafer scale fabrication. The first two involve STL and are used to form nanoscale features such as suspension...
In this work, a lithography-free approach for fabricating patternable nanopillars is reported. The key technique of the approach is to introduce a gap over the substrate by covering it with a cap, which contains through holes and the material on its lower surface has similar etching rate with the substrate. By this means, uneven etching of the substrate is induced under the through holes, consequently,...
A three-step model used for modeling and simulation of black silicon formation in DRIE (Deep Reactive Ion Etching) process is presented. It divides the plasma etching system into plasma layer, sheath layer and sample surface layer. At the same time, it combines quantum mechanics, sheath dynamics and diffusion theory together based on plasma environment to predict the probability distribution of etching...
Because of the unique mechanical and electrical properties, silicon was widely used in IC/MEMS devices for decades. However, it is difficult to fabricate high aspect ratio structures when the feature size scaling down to 7nm. In this paper, single crystal Si nano barrel with wall thickness 6.7nm and aspect ratio 50∶1 was achieved by top-down process. The fabrication was carried out by Electron Beam...
This paper reports a new lithography method using thin-film edge electrodes (TEEs) to collectively transfer nanopatterns by generating oxide on the substrate surface via an electrochemical reaction (ECR). Nanometric thick TEEs are formed on the sidewall of insulating stamping structures. ECR-based oxide patterns have the same width and shape as the TEEs because ECR is induced only between the conductor...
In the present work, the room temperature deposited silicon dioxide thin films are explored for the fabrication of microelectromechanical systems (MEMS) components and the surface texturing for crystalline silicon solar cell applications. The etch rates of as-grown oxide films are investigated in different concentration tetramethylammonium hydroxide (TMAH) and potassium hydroxide (KOH) solutions at...
We present a generic three-dimensional (3-D) integration method to fabricate suspended single crystalline silicon (SCS) MEMS arrays on CMOS. The method is based on transferring the SCS device layer of SOI on the top of CMOS. For general purpose, thin MEMS arrays with long supporting arms are demonstrated. The fabrication process is clarified in details. Mechanical reliability of the suspended structure...
This paper presents the results of experimental work on a low temperature through-wafer reactive ion etching (RIE) technique obtained in the course of development of a process that can be used in small sample processing for microelectromechanical systems (MEMS). Low temperature RIE are a crucial step for many dry MEMS fabrication processes, where can be used to fabricate silicon vias, trenches, and...
In modern society, the application of biosensor gains its popularity in various fields such as biomedical diagnostic, food technology, cancer therapies, pharmaceutics and environmental monitoring. New biosensing technology is needed to accommodate low cost sensor, able to give fast response, versatile technique and eventually more stable products. During the past decades, various researches work focusing...
Deep vertical etching of Si using hydrogen peroxide as oxidant and Au as catalyst has been studied in terms of relative reactant concentrations and catalyst morphology. The concentrations of hydrogen peroxide and hydrofluoric acid are highly important and the ratio of the same can be varied to achieve isotropic to highly anisotropic vertical etching. Catalyst morphology and positioning of the substrate...
We describe a through-silicon via (TSV) reveal process that uses direct Si/Cu grinding and metal contamination removal for the backside reveal of small-diameter (4 µm) TSVs. In this process, simultaneous grinding of Cu and Si was performed by using a novel grinding wheel (vitrified-bond type) and cleaning the grinding wheel with a high-pressure micro jet. Owing to the inelastic porous structure and...
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