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We report on vertically stacked horizontal Si NanoWires (NW) /»-MOSFETs fabricated with a replacement metal gate (RMG) process. For the first time, stacked-NWs transistors are integrated with inner spacers and SiGe source-drain (S/D) stressors. Recessed and epitaxially re-grown SiGe(B) S/D junctions are shown to be efficient to inject strain into Si/-channels. The Precession Electron Diffraction (PED)...
The Nano Wire (NW) CMOS technology is widely considered as a promising evolutionary solution of current FinFET technology. The main advantage of the nanowire transistors for ultimate CMOS scaling is their optimal electrostatic confinement. In this paper, the major assets of NW field-effect-transistors in leading-edge technology nodes are explained in details. For this purpose, electron (hole) transport...
To meet CD specifications required for 10nm and beyond Fully-depleted SOI devices (FDSOI) techniques alternative to EUV lithography are being developed. This article reports on the demonstration of Self-Aligned Dual Patterning (SADP), multi-beam electronic lithography and Directed Self-Assembly (DSA) to fabricate silicon fins with width < 10nm and high-k / metal gates with 11nm CD, or to shrink...
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