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The demand of small-feature-size, high-performance, and dense I/O density applications promotes the development of fine-pitch vertical interconnects for 3-D integration where microbumps are fabricated with Cu through-silicon via and under-bump metallization. Small dimension Cu/Sn bonding has to be developed to address the needs of increasing I/O density and shrinking pitch and size for future applications...
Processing of bump-less or embedded microbumps is introduced in this paper as an approach which enables scaling microbumps for below 10um pitches. Landing wafer is standard damascene process and in top wafer bumps are embedded in a soft backed polymer. Later during thermo-compression bonding this polymer is cured to bond two chips together. Process flow and results of TC bonding is discussed in this...
Foundry customers and makers of leading-edge devices are evaluating through-silicon via (TSV) for next-generation three-dimensional (3D) packaging. Scaling the diameter of the TSV is a major driver for improving system performance and cost. With smaller TSV diameters, back-to-front overlay becomes a critical parameter because via landing pads on the first metal level must be large enough to include...
In this paper a bump-less process is introduced in order to further scale down the pitch of microbumps. Electrical resistance measurement, Cross section SEM and mechanical characterizations show successful 3D stacking using proposed method.
Current TSV integration schemes include via-first, via-middle and via-last process flows. In this paper, a low thermal budget, 10ìm pitch and aspect ratio 10 (5ìm diameter, 50ìm depth) via-last TSV module is presented. The proposed via-last module is plugged in after the thinning module, with 50ìm thinned device wafers temporary bonded to a Si carrier, using Brewer Science Zonebond® material. After...
In this paper we report results and challenges of replacing Cu with Co as UBM (under bump metallization) in microbumps for 3D technology applications. Cobalt has softer and single IMC (intermetallic compounds) and according to calculations using Cobalt as UBM can reduce consumption of UBM material by solder which is attractive for sub 10um pitches of microbumps. However, cobalt oxidizes very fast...
To keep up with the pace of decreasing transistor channel length, the demand for smaller pitch size is pushing 3D IC research into new approaches for stacking. As the pitch size decreases, the thickness of interconnection also decreases. During stacking, a small misalignment may lead to poor interconnection or even connection failure. This has led 3D IC research to pursue higher alignment accuracy...
The cost of 3D process flows is one of the most important aspects for the broader adoption of 3D integration by the semiconductor industry. In this paper the processing cost of the features and components that enable 3D stacking is considered and compared. Different stacking approaches are considered: D2W, W2W and interposer-based stacking. Furthermore, the impact of processing yield and pre-stack...
In this paper a reflow process for fine-pitch micro-bumps is studied. A mathematical model for the reflow process is proposed and verified by experimental measurements. The influence of reflow profile parameters on the shape of micro-bumps, will be discussed using three commercial reflow ovens. Furthermore, measurement results of bump height variations after reflow over a 300mm wafer will be presented.
Large area silicon or glass interposers may exceed the maximum imaging field of step and repeat lithography tools. This paper discusses the lithographic process used to create a large area interposer on a stepper by the combination of multiple subfield exposures. Overlay metrology structures are used to confirm the relative placement of the subfields to construct the interposer. Routing lines from...
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