The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Current TSV integration schemes include via-first, via-middle and via-last process flows. In this paper, a low thermal budget, 10ìm pitch and aspect ratio 10 (5ìm diameter, 50ìm depth) via-last TSV module is presented. The proposed via-last module is plugged in after the thinning module, with 50ìm thinned device wafers temporary bonded to a Si carrier, using Brewer Science Zonebond® material. After...
This paper presents a 3D integration technology for imager application using wafer level permanent oxide to oxide bonding and TSV process for backside illuminated (BSI) CMOS image sensor (CIS). The process allows the stacking and electrical connection of two chips-illuminated imager chip on top of a readout and image processing chip by mean of a via last style TSV.
To keep up with the pace of decreasing transistor channel length, the demand for smaller pitch size is pushing 3D IC research into new approaches for stacking. As the pitch size decreases, the thickness of interconnection also decreases. During stacking, a small misalignment may lead to poor interconnection or even connection failure. This has led 3D IC research to pursue higher alignment accuracy...
In this paper we report on the silicon fabrication technology for developing of a Lab-on chip system. The main components in the system are mixers, micorector cavities, coarse filter and micropillar filters. Silicon fabrication technology offers distinct advantages in developing (LOC) platforms. It allows for very accurate control of size and uniformity of structures. Many different structures from...
A flexible neural implant was designed and fabricated using an novel integration approach that offers the advantages of both silicon and polymer based implants: high density electrodes and precise insertion on one side and mechanical flexibility suitable for reduced tissue strain due to micro-motion during chronic implantation on the other side. This was achieved by separating the device into silicon...
This paper presents a 0-level packaging technology for (RF-)MEMS implementing vertical feedthroughs or through-Si-via's (TSVs) and metal bonding. A thinned capping substrate (100μm thick) equipped with Cu-coated TSVs is bonded to a MEMS substrate. The vertical feedthroughs lead to a smaller footprint and make the package ready for 3D integration. The CuSn/Cu metal bonding provides a hermetic seal...
This paper reports the development of a novel 0-level packaging technology for (RF-)MEMS based on a collective cap transfer technique carried out on wafer scale. By taking advantage of the advances in temporary wafer support systems, it is now possible to fabricate very thin (below 100μm) capping dies and transfer these collectively in a single step at the wafer-level to a MEMS substrate.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.