The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Driven by minimized package size, cost as well as performance, wafer level package (WLCSP) is currently one of the fastest growing segments in the semiconductor packaging industry. Not as plastic BGA with a substrate interposer, WLP is a silicon chip directly mounted on printed circuit board (PCB) board. The large CTE(coefficient of thermal expansion) mismatch between silicon and organic leads to...
Drop test is transient and dynamic in nature. Therefore, explicit solvers such as ANSYS/LS-DYNA and ABQUAS Explicit are employed extensively for the free fall analysis [1-3]. To avoid complexity in modeling contact event, a simplified Input-G method was suggested [4-5]. However, the explicit algorithm suffers from poor numerical stability unless a very fine time increment is used, which means that...
As microelectronics is moving towards miniaturization, function integration and cost reduction, the device itself is becoming smaller while keeping same or even more functions. Silicon die with area less than 2×2 mm2 is common. This poses challenges for very small die handling and assembly. In another respect, high reliability is required for power packages especially for automotive application. During...
System-in-Package (SiP) which combines different chips and technologies into a single package is a viable solution to meet the rigorous requirements for today's mixed signal system integration. As the level of integration increases, challenges related to product manufacturability and reliability also increases. As a result, design for reliability using CAE (Computer-Aided-Engineering) or FEM (Finite...
With great feasibility and flexibility for growing I/Os, multi-chips and system integration, the emerging fan-out embedded Wafer Level BGA (eWLB) technology is regarded as a much more favorable packaging solution compared with its traditional counterparts, i.e. fan-in WLP or BGA technology. The relentless trend of ever increasing integrated circuit chip functionality and decreasing chip dimensions...
At millimeter wave (MMW) frequencies, high data rate applications such as kiosk downloading or Wireless HDMI require low cost and low power Systems on Chip (SoC) to address mass-market products and consumer expectations. Along with the developments of 60 GHz chipset solutions, low-cost antennas and package costs are obviously key factors to succeed in large volumes consumer applications. High Density...
Thermo-mechanical reliability is one of the major concerns for electronic packages, especially for power packages operating in extremely harsh environment. As the trends towards high density and function integration, advanced power device becomes more sensitive to environmental stress. Comprehensive study is needed from design, process to test towards robust power package with high reliability. In...
The associated significant loss with passive devices on silicon substrate is generally believed to be responsible for the presence of low quality factors, making it a poor candidate for the design of efficient output matching networks. STMicroelectronics has addressed this issue by coming up with a low-loss passive technology called IPD™ (Integrated Passive Devices) RLC06 technology, which is a passive...
In this paper, we will compare Cu wire and Au wire behavior during pull test and package reliability test through thermo-mechanical simulation. Relationship between wire pull test and package reliability test, i.e. thermal cycling, is also evaluated in term of die stress underneath the wire bond pad area. A new stress index concept is proposed to characterize the overall die stress level underneath...
Fan-out embedded wafer level ball grid array (eWLB) is a very promising packaging technology with many advantages in comparison to standard ball grid array packages and leadframe based packages because of smaller size, better electrical and thermal performance, higher package interconnect density and system integration possibilities at low packaging cost. It was successfully developed for medium and...
Drop performance for fine-pitch ball grid array (FBGA) assembly is one important issue because FBGA is widely used in handheld electronic products in which the solder joints are prone to failure when subjected to drop impact load during application. It is necessary to assess and improve the FBGA solder joint drop performance during design and engineering stage. The drop impact life model is needed...
With the fast growth of mobile phone market, image sensor and camera module production have skyrocketed in recent years. Semiconductor industry has been put a lot of effort in camera module design, assembly, and test technologies. The technology platform was mainly developed from normal BGA platform. However, camera module is more complex than normal BGA in design, assembly, and test. There were special...
In this paper, four-point cyclic bend test was conducted for PBGA (plastic ball grid array) assembly with Sn-3.5Ag lead free solder joint. Bending fatigue life of solder joint was recorded by measuring resistance of the designed daisy-chain for solder joints. Failure analysis was performed using dye penetration and the critical solder joint location was observed. Then, comprehensive finite element...
With the increasing requirement for lead-free solders, it is desired to know how different solder alloys affect on reliability of microelectronic assembly. Some fatigue life models for Sn-Ag-Cu (SAC) solder have been developed by researchers. The Ni-dopant lead free solder is increasingly used in electronic packages due to its good drop performance. Currently, it lacks the fatigue life model for Ni...
Board level drop test has become a key qualification test for portable electronic products in recent years. However, actual drop test and sample preparation are very expensive and time-consuming and requiring much manpower in measurement and failure analysis. Because of high demand for short time-to-market, drop test has become a bottleneck for semiconductor and telecommunication industry. In this...
The general tendency of the portable handheld electronic is to integrate more and more functionalities (phone, audio, video, Internet, wireless connections, etc.) in a size that is smaller and smaller (thinner devices per example). Thus, electronic components with a great level of miniaturization are needed, like wafer level chip scale packages (WL-CSP), to answer the market demand. In order to cover...
Solder joint reliability of IC packages under drop impact becomes a great concern for portable telecommunication devices such as mobile phones and PDAs. It is known that drop impact reliability of lead-free BGA solder joints is a critical challenge. With the development of advanced packaging applications such as system-in-package (SiP), package on package (PoP), embedded die, stacked die BGA, etc,...
This paper is an overview of applications of CAE (computer-aided-engineering) in design for package and board level reliability of system-in-package (SiP). CAE is an efficient tool for virtual prototyping of complex SiP to save the development time and cost with understanding on the physics of failures. The paper highlights on five major reliability issues frequently encountered in the development...
The demand for small, portable handheld electronic devices has led OEMs to reduce packaging sizes of all types and to create many choices to meet market demand. Wafer-level chip scale package (WL-CSP) is the newest technology to compete with CSP and near-CSP packaging, and has evolved under JEDEC MO-211 standard. This bare-die bumped package is able to reduce single-gate logic sizes by as much as...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.