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A simple analysis method for the estimation of data-dependent jitter (DDJ) in high-speed digital system using single pulse response is proposed. A frequency dependent model of a transmission line is considered to charaterize lossy channel properties, and the single pulse response is obtained with the model. The estimated DDJ in the single-ended transmission line is experimentally verified with the...
A deep silicon copper via process technology by damascene copper electroplating process has been developed and characterized for realizing through-wafer copper interconnection for MEMS and 3D wafer level packaging application. The paper further discusses various factors that affect the formation of deep silicon vias structures by using time-multiplexed inductive coupled plasma etch process, also known...
Wire bonding is an important method of interconnection in microelectronics. The micro welding of the contact pad to the gold wire is achieved by a thermosonic wire bonding process. Ultrasonic energy is known to soften metallic materials and hence when used in the wire bond process to decrease the flow stress similar to thermal energy. But experimental results shows for some lead frame designs neck...
Lead-free solders and soldering technology will be a revisited concern in microelectronics packaging challenges to meet the demands of wafers-level packaging and 3D packaging operations where greater demands will be made on soldering smaller pads sizes and the high expectations of solder joint strength and long-term reliability. This paper reports on the drop-in lead-free solder approach and will...
Integration of optical interconnects into printed circuit boards are seen as a promising solution to overcome challenges encountered with high frequency electrical interconnects. In this paper, we show some of the results obtained with development of high-speed 10-Gb/s parallel optical interconnects embedded on printed circuit boards. Multimode polymer waveguides are fabricated with commercially available...
Solder bumping usually represents the final stage in the WLP assembly process prior to dicing. Standard solder paste print and reflow techniques can be utilized but the resultant bumps invariably fall below specifications due to process limitations. More commonly, dedicated equipment is used for the placement of pre-formed solder spheres on the wafer pads. This paper details work undertaken to combine...
This paper is an overview of applications of CAE (computer-aided-engineering) in design for package and board level reliability of system-in-package (SiP). CAE is an efficient tool for virtual prototyping of complex SiP to save the development time and cost with understanding on the physics of failures. The paper highlights on five major reliability issues frequently encountered in the development...
Wafer mapping techniques originated at the wafer fab for wafer manufacturing process control and yield improvement as presented by T. Takeda (1994). Recently, inkless assembly processes have been becoming more and more popular for wafer fab process simplification and cycle time reduction, as well as the graded IC product sale under the pressure of IC manufacturing cost. However, not all of the packaging...
This paper describes the electrical design, packaging and specification challenges for high speed serial link interfaces utilizing clock data recovery and encoding protocols. Major design and modeling issues are discussed, such as attenuation, crosstalk, simultaneous switching, impedance control and intersymbol interference. Channel specification and characterization are important aspects of the total...
Portable electronic products demand integration of different functional chips like digital, RF and optical in a single module. Integration of multifunctional chips on silicon, organic and ceramic substrates for system in package is fast emerging technology. Presently chip level and package level stacked modules are primarily used for memory modules as presented by Val, (1994). In chip stacking technology,...
"Quilt packaging," (QP) a new paradigm for interchip communication, is presented. QP uses conducting modules that protrude from the sides of integrated circuits to affect an enhanced-speed, reduced-power method of interfacing multiple die together within a package or on a multichip module. The concept of QP is introduced along with a discussion of advantages over traditional system-on-chip...
There is a growing need to reduce the design cycle time of electronic packages to meet the consumer needs quicker. A design methodology to achieve this is to integrate signal and power-delivery analysis. In this paper, a transient simulation technique using S-parameters that does not violate causality is presented. Eye-diagram results are shown, with and without explicit delay extraction. Scalability...
Recently, research and industrial interest in underfill materials in electronics packaging has increased, especially in flip chip in package (FCIP) and wafer-level packaging (WLP). Underfill materials, typically comprising an epoxy resin matrix with silica particles, are required to improve packaging reliability in chip-level devices by reducing stress due to differences in the coefficient of thermal...
In this paper, the Taguchi optimization method is applied to obtain an optimal and robust design towards enhancement of board-level thermomechanical and drop reliability of a package-on-package stacking assembly under an accelerated thermal cycling test condition as well as a JEDEC drop test condition. An L18 (21 times 3 7) orthogonal array is arranged for the optimization of eight control factors...
To evaluate conjointly the effects of ambient temperature fluctuation and operation bias on the reliability of board-level electronic packages, a coupled power and thermal cycling test has been proposed. In this study, the sequential thermal-mechanical coupling analysis, which solves in turn the transient temperature field and subsequent thermomechanical deformations, is performed to investigate thermal...
Increased current density per bump is inevitable with the growing demand for miniaturization. Hence, the electromigration failure mode of bumps is critical to determine the bump current carrying capability. This paper presents the electromigration failure study of the copper pillar (Cu-pillar) bump and compared to that of the solder bumps. Our analysis shows that the Cu-pillar bump could handle higher...
Wafer level packaging (WLP) has many advantages, such as ease of fabrication and reduced fabrication cost. However, solder joint reliability of traditional WLPs is the weakest point of the technology. In this paper, a 0.4mm pitch Cu post type WLP has been developed for mobile computing. The Cu post type WLP has 440 I/Os and 12 times 12 mm die size. The initial design WLP has been fabricated and experienced...
Chip stacking has emerged as the best solution to reduce the packaging size (Karnezos, 2004). Several approaches are proposed by companies and laboratories and each of them presents specific advantages and drawbacks (Tummala, 2004). Today, major 3D applications are stacked memory DRAM, SRAM or flash. Moreover, cost acts as a brake on 3D expansion in SiP and further developments are necessary to reduce...
This paper provides a review of digital image correlation method for in-plane displacement measurements, as well as the variants of digital image correlation algorithms. After a broad literature review on digital image correlation, we found that it is clear that digital image correlation algorithms could be divided into two groups according to the image analysis performed in the spatial domain or...
This paper presents a novel process scheme for singulating microelectromechanical systems (MEMS) or CMOS devices that may be released or unreleased, which have fragile components and/or that have within or without in-plane structures. The process comprises spin coating of a polymer based protection material on the back and front of the device wafer, after attaching it to holder wafer. Such protected...
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