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Silicide gates are expected for application to high-speed VLSI's. TiSix/thin poly-Si structures were chosen for this study to realize low-resistive gates. For the purpose, the poly-Si sublayer should be as thin as possible. For 0.5μm CMOS technology, gate oxides are required to be as thin as 10 nm.
A test structure for reliability analysis of MOSFETs in CMOS inverters under DC and high frequency AC stress has been presented. It has an input pulse generation block with a ring oscillator, monitor inverter blocks and Kelvin connected selector switches. Detailed I – V characteristics of MOSFETs in the monitor inverters were measured and the degradation by HCI and BTI in nMOS and pMOS devices were...
Temperature distributions in three dimensional (3D) ICs were analyzed with a thermal simulation and compared with measured results of test 3D ICs, in which sensor p-n diode arrays and on chip heaters were embedded. The 3D IC consists of a top tier test chip and a 410 um thick bottom dummy chip. Both top tier chips and bottom dummy chips were fabricated by a standard 0.18 um CMOS process. The top tier...
A test structure for analysis of temperature distribution in CMOS LSI is presented. Fundamental thermal properties of LSI chip were measured and discussed with simulation results. The test structure consists of 24 sensor blocks, each of which has a resistor as an on-chip heater, a p-n diode array for temperature sensing and selector switches. Dependence of heating time and distance from the resistor...
A channel length engineering technique for optimization of primitive cells in standard cell libraries is effective for a leakage reduction method without significant increase of delay time, maintaining the same cell size. Reliability of NAND gates with series n-MOSFETs, which have modified channel length, have been analyzed under voltage stress condition with a test structure of ring oscillator implemented...
Subthreshold characteristics of CMOS devices become important for mixed signal SOCs (System On a Chip) [1]. Since matching of critical devices in important parameters such as IDsat (saturation drain current), VT (threshold voltage), gm (transconductance) and S (subthreshold slope) are important in CMOS analog circuit design, channel orientation and current flow direction should be carefully arranged...
Orientation dependence and asymmetry of VT (threshold voltage), gm (transconductance), S (subthreshold slope), and Ioff (off-state current at VG =3D 0 V) in 0.18 ??m n-MOSFETs were measured and analyzed. The test structure contains 8 different channel orientation angles of 0??/45??/90?? and three kinds of process conditions. Although VT, gm and S scarcely show particular anisotropy except for the...
A device with Si rich gate oxide has attractive characteristics such as visible electroluminescence (EL) and current-voltage (I-V) hysteresis. Consequently, the MOS devices with Si-implanted SiO2 have potentiality to integrate both the EL device and the high density non-volatile memories on a single Si CMOS LSI chip. Though visible EL from Si-implanted MOS capacitors have been reported, EL mechanisms...
A test structure with a wide channel width for analysis of hot-carrier-induced photoemission is presented and spectrum changes for 90 nm MOSFETs under DC (direct current) and AC (alternating current) operation are discussed. Comparing with DC operation, photon counts for higher photon energy increase under AC operation, and spectrum curves change with rise and fall time of gate pulse. The overshoots...
A supply voltage (VDD) independent temperature sensor circuit by a standard 90 nm CMOS process achieves the predicted errors about -1.0 to +2.0degC (-0.6 to +0degC) for the temperature range of -20 to +100degC (+20 to +80degC) for two-point calibration lines. This temperature sensor has a good tolerance to the change of VDD from 2.5 to 1.5 V, which corresponds to the measurement error of 0.9degC.
A channel length engineering technique for optimization of primitive cells in standard cell libraries is proposed and a test structure to analyze the operation performance and leakage current of 3-input NAND is presented. Since the topmost transistor (Nl) in the three series connected n-MOSFETs of 3-input NAND has the largest VDS, subthreshold leakage current can be reduced by optimizing a channel...
A test structure to analyze asymmetry and orientation dependence of MOSFETs is presented. n-MOSFETs with 8 different channel orientation and three kinds of process conditions were measured and symmetry of IDsat and IBmax with respect to the interchange of source and drain was examined. Although both IDsat and IBmax have similar channel orientation dependence, only IBmax in interchanged S/D measurements...
Electroluminescence (EL) characteristics of n + -polysilicon MOS capacitors with 50 nm Si-implanted SiO 2 were measured. The EL intensity is almost proportional to the gate current, and the EL efficiency is about 50-70 times larger than that of a MOS capacitor without Si-implantation. Although the EL spectra of MOS capacitors have a broad peak around 650 nm regardless of the Si-implantation,...
The current hump characteristics observed after large positive gate-voltage supply (write mode) in LOCOS-isolated n-MOSFETs with Si-implanted, 50 nm gate-oxide is analyzed. A MOSFET model which consists of an intrinsic FET in the center region of the channel and two parasitic FETs near the LOCOS-isolation edges is proposed and discussed. The intrinsic FET current steeply decreases near the induced...
Trench isolation technology with boron implanted vertical side-walls is presented andproved to be useful for completely suppressing humps in subthreshold current and controlling finely narrow width effects of n-MOS FETs. The technology is promising one to realize submicron trench isolation less than 0.5 ??m.
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