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The potential of optical lithography for production of VLSI circuits with design rules below 0.5 pm has been demonstrated by the performance of a first generation laser-based deep ultraviolet wafer stepper. The system, which has been described previously, consists of a fused silica reduction lens and illumination optics and a KrF excimer laser retrofitted to a commercial production tool [1-3]. It...
The increased packing density and the superior performance of scaled down VLSI circuits owes much to the improvement in the resolution by the optical lithography, which has already cleared the one-micron lithographic barrier.
As we enter the megabit era the demands on the performance of lithographic processes are dramatically increased. Achieving submicron resolution with sufficient line width control on subtrates with reflective topography is becoming a major problem.
There has been considerable recent interest in silicon-containing or silicon-receptive materials for use in improved-resolution optical and e-beam lithography. Inherent in such materials is the promise of trilayer lithographic performance in much simpler bilayer or even single-layer resist processes. Unfortunately, formulating photoresists with the necessary amount of silicon tends to dilute their...
Exposure requirements for size control of high density features results in overexposure of isolated or low density lines and features. Use of positive photoresist results in low density feature shrinkage under these conditions. This paper presents a simple methodology of automatic addition of variable biasing to features depending on local circuit density using software manipulation of the circuit...
In both photo lithography with reduction projection printings and electron beam lithography with direct writing techniques, their resolutions are limited by the proximity effect caused by the diffraction in photo lithography and electron backscattering in electron beam lithography, respectively. To evaluate and clear them, computer simulation is very useful for sub-micron pattern fabrications.
Several self-aligned bipolar technologies have been developed to achieve high-speed and low-power dissipation bipolar LSI's (1×2×3). These technologies reduce collector-base capacitance and extrinsic base resistance. In order to realize much high-speed bipolar LSI performance, it is necessary to reduce collector-substrate capacitance and wiring capacitance simultaneously, although it is rather difficult.
Low temperatures and short times are essential requirements of future VLSI processing and the use of plasma in conjunction with single-wafer lamp heating is a major step to realize this goal, In-situ multiprocessing reduces contamination and enhances yield. Reproducible growth of thin oxides in hot-wall furnaces is difficult due to long transient times and constant furnace temperatures. Since furnaces...
Oxide lifetime extrapolation using log(tBD) or better log(QBD) against 1/ Eox plot is more accurate and has a theoretical basis. Highly accelerated oxide test completed in seconds appears to be feasible. The acceleration factor is also a function of the severity of the oxide defect. Extrapolation of defect-related break-down lifetime can be performed assuming an effective oxide thinning for defects.
We report, for the first time, excellent device characteristics of both n and p-channel (complementary) IGFETs with very thin nitride/oxide stacked gate insulators (10–14nm equivalent oxide thickness). The top nitride layer (as thin as 4nm) is effective in preventing boron penetration from the p+-poly gate to the channel. The threshold voltage instability and channel hot carrier effects are controlled...
Reactive ion etching (RIE) is widely used for fine pattern transfer in VLSI. However, the dry etching induces damage and contamination onto the etched surface. After SiO2 RIE on Si for contact holes with CF4-H2 gas, the Si surface is covered by thin fluorocarbon film, and lattice damage is induced in the Si substrate [1], Furthermore, it is also well known that thin halocarbon film covers the side...
During development phases of a 1 Mbit DRAM, two distinctive types of bit fail maps were frequently observed. ‘Top/Bottom Fails’ (TBF) were groups of bit-line fails located at the top and/or bottom of arrays. ‘Curtain Fails’ (CF) were U-shaped streaks occurring in the interior of the array (see Fig 1). The problem was highly variable in its occurrence but the overall yield limit from this mechanism...
In recent years, the performance of bipolar transistors has been improved through the use of down-scaling and polysilicon base technologies. However. scaling1 down to under a quarter of a micron has been found to be very difficult because of the need for precise control of emitter size and junction depth. In response to this problem, a now transistor structure is considered to study the limitations...
Polysilicon emitter contacts play an increasingly important role in high-speed npn bipolar transistors, particularly for emitter thicknesses of 0.1 μm or less. When optimizing these contacts, both the emitter resistance and the base current must be considered [1,2]. These two parameters are strongly dependent on the morphology of an interfacial layer between the poly and the single-crystal silicon...
Due to the continuous reduction of pattern size in VLSIs, there is an urgent problem in vertical scaling for MOS and bipolar devices. Especially for high speed bipolar VLSIs, a very thin base with a high carrier concentration is required because the minimum delay at high power dissipation is predominantly determined by the intrinsic base width. A base region is conventionally fabricated by boron ion...
Alpha-particle-induced soft-error. first reported for 16kb MOS DRAMs in 1979(1], has developed into the most critical design factor for 1 or 4Mb DRAMs. Further, with reduction of device dimensions. soft-error becomes critical in high speed bipolar RAM. especially high density RAMs in excess of 16Kbs[3], [4].
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