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The thermal resistance of a three-dimensional (3D) chip stack has been experimentally clarified by authors [1-5] and an additional cooling solution is strongly required to achieve various structures of 3D chip stacks. Especially, when a high heat dissipating chip is located as a bottom chip, cooling from the bottom side of chips (in other words, from the laminate (substrate) side) is identified to...
When a 3D chip stack is composed of some memories and a logic device such as processor, the logic device has been assumed to be located as a bottom chip in wide I/O and HBM applications. On the other hand, for high-end server applications, a processor needs to be located as a top chip because it needs to be cooled efficiently. In this case, many Through Silicon Vias (TSVs) are necessary in a memory...
Cognitive computing is capable of machine learning, recognition and proposal. It has a great potential to make human life richer, more productive and more intelligent. For the realization of the cognitive computing, an efficient and scalable non-von Neumann architecture inspired by the human brain structure has been developed and a device which demonstrates the concept was also built. This device...
The thermal resistance of a three-dimensional (3D) chip stack has been experimentally clarified by authors [1–6] and an additional cooling solution is strongly required to achieve various structures of 3D chip stacks. Especially, when a high heat dissipating chip is located as a bottom chip, cooling from the bottom side of chips (in other words, from the laminate (substrate) side) is identified to...
A dual-side cooling topology is proposed that is achieved by embedding a power insert into the organic substrate of a chip or chip stack. The power insert consists of vertical copper lamellas supporting lateral current feed in addition to vertical heat dissipation at minimal electrical and thermal gradients. The lateral current feed capability is key to enable the introduction of the cold plate on...
In conventional SiP (System in Package), several semiconductor chips had been 2D arranged in an interposer and a mother board. However, it is difficult to downsize and improve the performance of electronic devices due to that large area is occupied by the chips. Recently, 3D packaging technology has been investigated to reduce size of devices and to improve performance of semiconductor devices [1-11]...
Recently, the downsizing and high-performing semiconductor packages have been developed and 3D packaging has been spurred research into reliability of TSV (through silicon via) [l]-[9]. In conventional SiP (System in Package), several semiconductor chips had been arranged in a plate. It is difficult to correspond to downsizing and high-performing of electronic devices because that large area is occupied...
For the thermal management of a three-dimensional (3D) chip stack, cooling from the bottom side of chips (in other words, from the laminate (substrate) side of chips), in addition to conventional cooling from the top surface of chips, is proposed. For cooling from the bottom side of chips, it is essential to consider the trade off among thermal, electrical and mechanical performance. Firstly, the...
Thermal stresses around void in TSV (Through Silicon Via) structure in 3D SiP were discussed under the conditions of device operation and reflow process by using FEM (Finite Element Method). In case of the condition of device operation, equivalent stress around void inside Cu TSV was estimated at around 100 MPa. It showed the low possibility for low cycle fatigue of Cu TSV under device operation because...
The stresses of TSV (Through Silicon Via) and Si chips in 3D-SiP were discussed with a large scale simulator based on FEM (Finite Element Method), ADVENTURECluster. In this study, the stacked layer structure of Si chips is modeled accurately. Thermal stress simulation for TSV structure in Si chips is carried out under thermal loads due to device operation and reflow process. In case of device operation,...
It has been experimentally clarified that one of the thermal resistance bottlenecks of a three-dimensional (3D) chip stack is interconnection (solder bumps and underfill) between stacked chips. High thermal conductivity underfill, which we call high thermal conductivity inter chip fill (ICF), is expected to reduce the thermal resistance of interconnection efficiently, because the area which is occupied...
3D organic packages with three-die stack were evaluated by finite element analyses and thermal cycle tests. The thermal cycle tests with different silicon thickness configurations were performed. The die-stack test vehicles with thin top die (150μm) did not show any failures during the 2000 cycles of thermal cycle tests. However, failures were detected for the test vehicles with thick top dies (400μm)...
In ASET (Association of Super Advanced Electronics Technologies), the thermal resistances of three-dimensional (3D) chip stacks have been measured by using 3D stacked thermal test chips which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. The equivalent thermal conductivity of interconnection between stacked chips (SnAg + Cu post) and that of TSV...
The thermal resistance of a three-dimensional (3D) chip stack is evaluated, based on the measured thermal resistances of 3D stacked thermal test chips which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. It is discussed how much heat generation of a 3D chip stack is permitted, when a conventional cooling from the top of a 3D chip stack is assumed...
The exascale computing is required in the Era of Big Data. In order to achieve this demand, new technology innovation must be required and packaging scaling including 3D-IC with TSV (Through Silicon Vias) is one of most promising technology. To increase the total bandwidth, the fine pitch die to die interconnection is necessary. Micro-bumping, thermally enhanced underfill and advanced interposer technologies...
Packaging of 3D die stacks on organic laminates is a low-cost approach to achieve devices with high density I/O and short wiring delays. However, the large mismatch in coefficients of thermal expansion between components in the package causes deformation and high stress in the constituting elements. The components such as thin dies, metal through silicon vias, fine-pitch interconnections are susceptible...
In this study, the required heat transfer coefficient of heat sink is quantitatively shown by steady heat conduction simulation. Maximum principal stress of silicon and equivalent stress of the TSV are obtained from thermal stress simulation.
The relation between maximum temperature in Si chip and varied heat transfer coefficients of heat sink is shown in Fig. 5. Maximum temperature for device operation was assumed to be 85 °C. Heat transfer coefficient of heat sink at device operation is estimated to be 4.5W/m2K by quadratic approximation of least square method. Maximum temperature of 3D SiP was almost 85 °C and uniform temperature distribution.
We present a methodology for the formulation of percolating thermal underfills (PTUFs) with enhanced thermal conductivity for efficient heat dissipation between dies in 3D chip stacks. The methodology is based on the centrifugal filling of micron-sized powders in a confined space (defined by a solder ball array) to form a percolating particle bed, and on the formation of enhanced thermal contacts...
For the thermal management of three-dimensional (3D) chip stack, its thermal resistance needs to be clearly understood. In this study, 3D stacked test chips are fabricated, which are implemented with PN junction diodes for temperature sensors and diffused resistors for heating. At SemiTherm2011, the equivalent thermal conductivity of the interconnection, including BEOL (Back-End-Of-the-Line, wiring...
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