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The parasitic capacitances in Vertical FET(VFET) are investigated. Vertical device has additional parasitic capacitance compared with lateral device because of deeply contacted drain metal. This parasitic capacitance degrades the performance of the device. In this study, tri-gate channel VFET which eliminates the additional parasitic capacitance without broadening the device area is proposed.
In this work, we compare parasitic components between lateral nanowire-FET (LFET) and vertical nanowire-FET (VFET) based on ITRS 2015 using 3D Technology Computer-aided Design (TCAD). We compare the parasitic resistances and capacitances in accordance with channel thickness. Further, we analyzed the effects of parasitic components on device performance and proposed the direction of device scaling.
In this paper, the dual-k spacer of nanowire-FET is investigated using a variety of materials compared with single spacer. The proposed structure shows significant improvement of delay characteristics and better electrostatic controllability than those of single spacer.
In this paper, we have investigated RC delay not only on single channel but also on multi-channels in lateral FET (LFET) and vertical FET (VFET). It has verified that there is always constant for SCEs regardless of the number of channels. Since all structures have the same gate length and spacer length, they have the same gate controllability. On the other hand, RC delay depends on the structure....
Self-heating effects (SHEs) were studied on the vertical nanoplate-shaped gate-all-around (GAA) FETs (vNPFETs) as a target of 5nm node technology. The thermal properties are compared between face-up and face-down configuration. Decreasing the channel width is vulnerable to both configurations in terms of SHEs due to the reduced area of heat dissipation. It is well known that the SHE is alleviated...
In this paper, the Self-Heating Effects in Vertical FETs(VFET) have been investigated according to device geometry. It is demonstrated that the temperature of the device increases by using a low-k dielectric and an air gap between the metal lines. In addition, when air spacers are used, the lattice temperature is further increased and the on current reduction ratio increases compared to the common...
Accurate evaluation of Self Heating Effects in highly down-scaled devices becomes essential for improved performance and reliability. However, complex structure of BEOL causes analysis of SHEs to be difficult To remove the difficulty, based on Rent's rule to obtain interconnect density function, effective thermal conductivity of BEOL versus metal volume density and average aspect ratio (p) was calculated...
Device characteristics in the operating region, subthreshold region, and OFF region were analyzed to propose optimum design guideline for nanowire FET. First, the research was focused on the structure of extension region in perspective of RC delay. Also, Subthreshold Swing (SS) and Gate Induced Drain Leakage (GIDL) were investigated because these characteristics are greatly affected by the structure...
In this work, Work-Function Variation (WFV) are studied on 5 nm node gate-all-around (GAA) Vertical Nanoplate FET (NP VFET) in 6-T SRAM using Technology computer-aided design (TCAD) simulation. As WFV effects become intensified, we investigate the WFV effects for an accurate guideline with regard to grain size (GS) and channel area of NP VFET in SRAM bit cells.
In this paper, the two Negative Bias Temperature Instability (NBTI) framework components are divided with interface trap generation (Δ Vit) and hole trapping in pre-existing defects (Δ Vht). The threshold voltage shift (ΔVT) contribution is verified by two divided components and studied independently. The impact of inter layer (IL) thickness is simulated under NBTI stress using technology computer-aided...
In this paper, we analyzed the characteristics of dominant failure mechanisms in the erased (ERS) state of sub 20-nm NAND Flash memory with an accurate compact model. As a result, it was observed that various charge loss and charge gain mechanisms are mixed together. While the detrapping and the interface trap recovery (Nit) mechanism contribute to the charge loss, the trap-assisted tunneling (TAT)...
This paper provides the simple design guideline of negative capacitance FET (NCFET). By considering average slope in polarization of a ferroelectric (FE) material according to electric field, simple design guideline was suggested to find the optimal thickness of FE material in NCFET where SS becomes 60 mV/dec. As the thickness of FE material increases, subthreshold swing (SS) becomes improved until...
In this paper, we investigate the characteristics of npn device as a candidate for RRAM selector. npn selector shows high current density and selectivity which are key metrics for the bidirectional select device. We confirm that length and doping concentration of base and emitter region can be varied to optimize the characteristic of the selector. In addition, we observe AC characteristic with 10...
Mixed mode TCAD simulation using hydrodynamic transport model was performed for SRAM cell composed of 90Å silicon Bulk-FinFET. In case of worst-case trapping combination in SRAM and at high temperature (375K), read static noise margin (RSNM) is reduced by 16.1% compared to the case with empty trap and at 300K. In addition, regarding statistical variability including work function variation (WFV),...
In this paper, we investigate the impact of line edge roughness (LER) combined with random telegraph noise (RTN) induced by carrier trapping on threshold voltage and stability of SRAM cells with 70 Å nanowire FETs. It is found that LER combined with RTN boosts VT fluctuation more than the case with the single noise source. Its effect can limit aggressive scaling seriously.
As mutual-capacitive touch-screens expand their application area to various information devices, better controllers are in demand for larger, thinner, lower-cost touch-screen panels (TSP), and in-cell/on-cell touch displays [1]. In order to gain higher sensitivity from such large and noisy TSPs, numerous parallel analog circuits are integrated on TSP controllers. Many solutions to cope with harsh...
Capacitive touch-screen technology introduces new concepts to user interfaces, such as multi-touch, pinch zoom-in/out gestures, thus expanding the smartphone market. However, capacitive touch-screen technology still suffers from performance degradation like a low frame scan rate and poor accuracy, etc. One of the key performance factors is the immunity to external noise, which intrudes randomly into...
A high SNR capacitive touch screen panel (TSP) readout IC is designed. In this paper, Orthogonal Frequency Division Multiple Sensing method is proposed to enhance frame scan rate. Capacitor-less Trans-Impedance Amplifier and Direct Digital Frequency Synthesizer based on Harmonic Rejection Ratio DAC is proposed to save chip area. The prototype IC with 0.18um CMOS achieves 70dB SNR for a finger and...
The conduction mechanism in Ti/Si3N4/p-Si memory stack is described. In order to analyze the conduction mechanism, we measured the I-V characteristics in voltage sweep mode and conducted I-V curve fitting. And the temperature dependence in Ti/Si3N4/p-Si stacked cell is also investigated because we cannot claim the conduction mechanism just based on the I-V curve fitting. From I-V curve fitting and...
In this paper, we measured four-level Random Telegraph Noise (RTN) in Gate Induced Drain Leakage (GIDL) current of Metal Oxide Semiconductor Field Effect Transistor (MOSFET). Using RTN measurement data, we extracted fundamental parameters of each trap, such as the trap depth (xT) and energy level (ECox-ET). To correctly interpret capture and emission process, capture cross section (σc) of the traps...
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