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In a “call for leadership” panel at ISSCC, we will be seeking leaders' perspectives on the future of discontinuous innovation in the semiconductor industry. An ensemble of visionaries, experts and CEOs will discuss the opportunities and challenges for innovation in our industry. Of primary concern is the reduction in funding available for new semiconductor ventures. Are the escalating NRE costs of...
This session demonstrates design techniques to realize data converters with unprecedented combinations of speed, resolution, and power efficiency in advanced CMOS technologies. Papers in this session include a time-interleaved ADC with a sampling rate up to 90GS/s, a time-interleaved DAC at 4.6GS/s conversion rate, and a time-based 2.2GS/s ADC. These converters are essential for systems enhanced by...
State-of-the-art wireless systems implemented in low-cost, deep-sub-micron CMOS processes support a wide range of applications including mm-Wave ranging, Gb/s communications in 60GHz/5GHz bands and cost-sensitive cellular communications. This session includes one radar receiver paper, three state-of-the-art 60GHz transceivers supporting 2 to 28Gb/s, the first reported fully integrated 802.11a/b/g/n/ac...
In recent years the use of CMOS technology has enabled the integration of low-cost, low power and multi-standard RF transceivers. While architectural innovation has allowed most of the transceiver blocks to be integrated in a single chip, full compliance to wireless standards still demands that many off-chip components be added to achieve the overall solution. The papers presented in this session...
High-speed track-and-hold amplifier (THA) circuits are critical for high-speed, high-resolution data converters, particularly in emerging 100Gb/s optical communication systems. High-speed CMOS analog-to-digital converters (ADCs) have been demonstrated to 56GS/s, but the linearity tends to rapidly degrade at high frequency [1]. The use of a high-speed THA can broaden the frequency response, improve...
This paper presents a 576b LDPC decoder test-chip designed using a charge-recovery logic family. The chip has been fabricated in a 65nm CMOS process and relies on 16 integrated inductors to achieve energy-efficient operation by recovering charge from gate fanouts. When self-oscillating at 821MHz, the chip recovers 51.4% of the energy supplied to it. In terms of device count, this chip is more than...
System power consumption will drive the architecture of future computing systems. From cloud-connected smart phones to the first exaFLOP supercomputers, systems that are the best at managing and minimizing power consumption will hold a key competitive advantage. At the same time, wireline communication bandwidth requirements within these systems will continue to grow exponentially, driving per-lane...
Cloud computing requires interconnect solutions for distances ranging from tens of kilometers to less than one meter, driving the demand for advances in both optical links and copper-based Ethernet PHYs. The power consumption, cost, data-rate, and density of these designs must all be improved simultaneously, driving innovation in both the circuit and system architectures. This session includes 9 papers,...
With the rise of cloud computing and Big Data, data centers are an important counterpoint to rapid growth in the mobile market. Building cost-effective, efficient computing infrastructures is a challenge that starts with technologies that ISSCC knows so well (processors, I/O, memory, etc.), but also encompasses system and customer-centric issues such as cooling, power delivery, and total cost of ownership...
Conventional analog PLLs do not scale well with process when compared to alldigital PLLs due to several substantial building blocks such as the loop filter and charge pump (CP). To achieve the required phase noise, the in-band noise is typically suppressed by increasing CP current and loop filter size, while the out-of-band noise is reduced by improving VCO tank Q; both lead to increased die area...
Strong market demands of diverse non-volatile memory technologies show continuing increase in density, reliability, and performance. This year the leading edge process node for NAND Flash is scaled down to the minimum feature size of 16nm, and three-dimensional vertical NAND has been demonstrated. In addition, Flash controllers contribute to the higher reliability and performance on such advanced...
VCOs and PLLs are at the heart of communication systems. They are critical for almost all RF systems such as receivers, transmitters, imagers, and radars. This session starts with three highly digitized frequency synthesizers, including multiplying DLL/PLLs with fractional-N operation and a direct-digital frequency synthesizer. The fourth paper demonstrates a mm-Wave PLL based on a subsampling technique...
The Plenary Session begins with opening remarks and a welcome to attendees from the Conference Chair, Anantha Chandrakasan. Then, the Program Chair, Trudy Stetzler, introduces the first two of four plenary speakers. Following the second plenary speaker, the Session pauses for an Awards Presentation moderated by the Conference Chair. Following a short break, the third and fourth plenary speakers are...
Three-dimensional (3D) stacking integration is offering many product benefits to SoC and memory: performance enhancements, product miniaturization and cost reduction. Besides, image sensors featuring 3D stacking of a specialized image sensor layer on the top of a deep submicron digital CMOS have just come to the market. The objective of this forum is to present applications and details of process...
The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions. Consequently, the memory bandwidth requirement has also been increasing, requiring a next-generation mobile DRAM standard. In this paper, we present a power-efficient LPDDR4 SDRAM operating at 3...
Ventilator-associated pneumonia (VAP) is the most frequently acquired infection among patients that receive mechanical ventilation in the intensive-care unit (ICU). The mortality rate for VAP lies in the 20-to-50% range and could be even higher in some ICUs. A standard operation procedure to VAP treatment includes a sequence of chest radiography, sputum gram stain, sputum culture, and empiric therapy,...
To meet the challenges of dynamic power requirements of diverse electronic applications, both high performance switched-mode and switched-capacitor DC-DC converters are indispensable. In the first part of the session, switched-mode power converters catering to multi-core SoCs (system-on-chips) are presented. They have to switch at frequencies into the 10MHz regime for small form factor, to have multi-phase...
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