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Welcome to the ISSCC 2013 Digest DVD. From its beginning in 2005, this DVD is a response to the many requests we have received over the years for Conference-time search-ability.
What you see before you this year, is the result of many years of continuous iterative refinement of the submission process and information processing. This year, however, as the economic situation persists, we continue to provide a reduced-featured Digest, in which the continuation pages (typically including a micrograph and occasionally summary data) have been eliminated from the print version (only),...
It is my pleasure to welcome you to the 60th International Solid-State Circuits Conference. The Conference continues its outstanding tradition of presenting the most-advanced and innovative work, both from industry and academe, worldwide, in the area of integrated circuits and systems. This year, the geographical distribution of the accepted technical papers, again, illustrates the global character...
The Plenary Session begins with opening remarks and a welcome to attendees from the Conference Chair, Anantha Chandrakasan. Then, the Program Chair, Bram Nauta will introduce, in turn, the first two of the four Plenary speakers, who will provide their visionary presentations. The second Plenary talk is followed by the Awards Presentation, moderated by the Conference Chair. Following a short break,...
Anyone wishing to drive advances in computing technology must carefully negotiate key trade-offs. First, reducing power consumption is increasingly critical. Consumers want improved battery life, size, and weight for their laptops, tablets, and smartphones. Likewise, data-center power demands and cooling costs continue to rise. Concurrent is the demand for improved performance that enables compelling...
Through advances in semiconductor and software technology, consumer-electronics products have achieved extraordinary performance, advanced functions and low-power operation at affordable prices, making our lives more convenient and enriched. In the future, all consumer-electronics products will cooperate over the network and connect to the cloud. The cost performance at the overall system level will...
Chip makers are increasingly concerned about the shrink and cost. This concern drives different lithography solutions for different products. Two major trends can be observed: aggressive adoption of EUV, or aggressive extension of immersion. Further cost reduction could be achieved by introducing 450mm wafers.
Faraday's Law of induction gave us generators, motors, telegraph, telephone, etc. The vacuum tube gave us long-distance telephone, radio, hi-fi audio, television, and early computers. Microcircuits have given us personal computers, cell phones, the Internet, and GPS positioning.
With the continuing growth in and demand for data communication bandwidth, designs targeting standards such as 100GbE, OIF CEI-25G, SONET OC768, and beyond are increasingly important. The transmission and reception of such high data rates through challenging electrical channels requires sophisticated yet energy-efficient equalizer design techniques. This session includes 8 papers, describing 32Gb/s...
Standards such as OIF CEI-25G, CEI-28G and 32G-FC require transceivers operating at high data rates over imperfect channels. Equalizers are used to cancel the inter-symbol interference (ISI) caused by frequency-dependent channel losses such as skin effect and dielectric loss. The primary objective of an equalizer is to compensate for high-frequency loss, which often exceeds 30dB at fs/2. However,...
Given the continuously climbing data rates of high-speed I/O's, equalizer circuits—and particularly decision-feedback equalizer (DFE) designs—are being pushed to operate at ever-higher speeds. At 20 to 40Gb/s data-rates, loop-unrolled DFEs are widely adopted to relieve the feedback timing constraints of the initial tap(s) [1]. However, loop-unrolling introduces additional delay into the critical paths...
The introduction of 40Gb/s networks, spurred by 40Gb/s WDM growth, can alleviate bandwidth bottlenecks of Internet infrastructure while simultaneously reducing operating costs. Increasingly, standard CMOS technology is used to enable transceiver speeds [1–5] previously achievable only by using expensive bipolar technology. However, at 40Gb/s, limited channel bandwidth coupled with stringent receiver...
Demand for bandwidth in metro networks and data centers has fueled the deployment of 10Gb/s traffic over legacy data links, such as backplanes (KR) and multimode fiber (MMF) [1]. Under severe channel impairments, an ADC-based receiver with a DSP backend provides robust performance, especially for MMF applications, due to the complexity of the channel pulse response and the dynamic nature of the channel...
In next-generation communication standards, such as OIF CEI-28G-SR and CEI-56G-VSR, the data rate has to be doubled or quadrupled compared to the current standards. Though transceivers for a data rate over 25Gb/s have been reported [1–3], designing clock-generating circuits for the receiver front-end is a significant challenge. In a phase interpolator (PI) commonly used in conventional receivers for...
Serial-link transmitters are widely used in applications like optical transceivers and multi-gigabit Ethernet. At tens of Gb/s, the operating range of bit-rates is narrow; limited by the speed of the multiplexing and the setup and hold time constraints of the last stage in the serializer. This constraint leads to using delay-matching buffers [1] or delay calibration loops [1–2] to guarantee that timing...
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