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Temporal unreliability due to aging, such as Negative-Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) effects etc., in the CMOS circuits may not appear just after the chip production, instead it becomes apparent when it is used under certain workload and environmental conditions over time. Identifying aged paths that may become critical to circuit performance, is a real challenge...
Localized small delay defects, for example due to degraded transistor drive strength caused by a broken fin, are a growing concern in current FinFET and emerging gate all around (GAA) technologies. Such defects are currently targeted by timing-aware Transition Delay Fault (TDF) tests that aim to test the target nodes along the longest path. The resulting tests often require considerable test generation...
With an increasing number of complex cells in today's VLSI designs, intra-gate opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOF) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient...
Negative bias temperature instability (NBTI) is a key reliability issue in deep sub-micron technology nodes. Identifying NBTI induced high variability timing-critical paths in stipulated design cycle time is a real challenge for System-on-Chip (SoC) designers. Firstly, we identify those device parameters that must be considered while performing statistical simulations to estimate maximum path delays...
Opens are known to be one of the predominant defects in nanoscale technologies. Especially with an increasing number of complex cells in today's VLSI designs intra-gate opens are becoming a major problem. The generation of tests for these faults is hard, as the timing of the circuit needs to be considered accurately to prevent the invalidation of the generated tests through hazards. Current test generation...
Cell Aware testing (CAT) has received much publicity in recent years, with several reported success stories in screening defects missed by traditional stuck-at and transition delay fault (TDF) testing. For example, at ITC 2012, Hapke et al. reported 885 DPPM test escapes in a 32 nm notebook processor part despite industrial strength stuck-at and 5-detect TDF testing. Significant additional fallout...
The wide variation in process parameters now being observed in advanced semiconductor processes can sometimes cause the electrical impact of subtle manufacturing defects on observed signals during post manufacturing tests to remain within the acceptable range set to ensure viable manufacturing yields, thereby masking defect detection. Such undetected manufacturing flaws can potentially cause functional...
In the recent past, Physically Unclonable Functions (PUFs) have been proposed as a way of implementing security in modern ICs. PUFs are hardware designs that exploit the randomness in silicon manufacturing processes to create IC-specific signatures for silicon authentication. While prior PUF designs have been largely digital, in this work we propose a novel PUF design based on transfer function variability...
In some complex deep sub-micron designs, the variations in interconnect delay has a significant impact on the production yield of the product. In this paper, we develop a theoretical explanation for the unexpectedly higher process related timing variability shown by long interconnects that are driven by high drive strength gates. This gets even worse due to conventional gate delay variability and...
Recent test studies on volume production data suggest that a significant number of CMOS open defects remain undetected by commonly applied TDF timing tests, potentially leading to high defectivity in the shipped parts. This has focused attention on developing tests that explicitly target open faults, in particular transistor stuck open faults (TSOFs). However, while TSOFs cover all open faults in...
The process of testing Integrated Circuits involves a huge amount of data: electrical circuit measurements, information from wafer process monitors, spatial location of the dies, wafer lot numbers, etc. In addition, the relationships between faults, process variations and circuit performance are likely to be very complex and non-linear. Test (and its extension to diagnosis) should be considered as...
We make the case that TDF timing tests, even when aggressively applied at-speed, uniquely detect mostly open defects within standard cells. The majority of these defects can also be detected at somewhat slower test speeds without the risk of unnecessary yield loss from test noise. Meanwhile, many other opens that can cause operational failures remain undetected by current LOC, and even LOS, TDF tests...
Transition detectors have been widely employed for online error and metastability detection, including in Better-Than-Worst-Case (BTWC) timing design of microprocessors that are designed to allow occasional timing errors. In such applications, the area overhead introduced by the transition detectors is a major concern because they may need to be incorporated in almost all the flip-flops in a large...
Scan based transition delay fault (TDF) tests are generally applied in the launch-on-capture (LOC) mode because the scan enable control signal broadcast to all flip-flops on the die is expensive to implement as a fast switching signal needed to support at-speed launch-on-shift (LOS) tests. However, there is mounting evidence that even when applied at much slower speeds, LOS tests often detect a significant...
Open defects in CMOS circuits can cause a gate output to go into a high impedance, or “floating” mode, for some input patterns. Since such defects display (large) delay fault behavior, they are commonly assumed to be covered during structural testing by scan based TDF timing tests. TDF tests are generally applied in the launch-on-capture (LOC) scan test mode to avoid “overtesting” the circuit timing...
Better-than-worst-case timing design methodologies aim at increasing throughput by speeding up the clock to the point where circuit timing margins are reduced to zero and even beyond. In low power designs such as Razor, this efficiency improvement is translated into power savings at a fixed operational clock rate through adaptive and dynamic voltage scaling. The main challenge in such designs is the...
Recent studies indicate that a significant number of very large delay faults that increase circuit path delays several fold, remain difficult to detect and are only discovered by very carefully crafted and comprehensive two-pattern tests, e.g. cell aware tests. A likely source of such large delays in CMOS is stuck-open faults. These can sometimes still allow the circuit to reach the correct logic...
Better-than-worst-case timing designs such as Razor introduce shadow flip-flops triggered by a delayed clock in parallel to the functional flip-flops for timing error detection through duplication and comparision. This arrangement suffers from the "short path" problem, whereby the activation of paths shorter than this timing skew can cause false errors to be flagged. The traditional solution...
Hazards have been known to have the potential to invalidate tests for stuck-open faults in CMOS circuits. In this paper we show that hazards can also predictably allow the detection of stuck-open faults that may be undetectable by traditional TDF launch-on-capture (LOC) scan delay tests. Importantly, the detected open faults are not redundant, and can in fact be activated in normal functional operation...
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