The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Todays' Integrated Circuits (ICs) are starting to reach the physical limits of CMOS technology. Among the multiple challenges arising from technology nodes lower than 20nm, we can mention high leakage current (i.e., high static power consumption), reduced performance gain, reduced reliability, complex manufacturing processes leading to low yield and complex testing procedures, and extremely costly...
Presents the introductory welcome message from the conference proceedings. May include the conference officers' congratulations to all involved with the conference event and publication of the proceedings record.
Fault injection is a well-known technique to evaluate the susceptibility of integrated circuits to the effects of radiation. In this work, an existing emulation-based methodology is extended, updated and improved under the name of NETFI-2. Preliminary results show that NETFI-2 provides accurate measurements while improving the execution time of the experiment by more than 300% compared with other...
Electronic systems functionality degrades when these systems are operating in harsh environments such as those where they are exposed to ionizing radiation. Understanding and measuring these effects is extremely important in order to design systems that can operate reliably. This work discusses experimental data of heavy ion and x-ray radiation effects on a Commercial-Off-The-Shelf (COTS) low-cost...
The miniaturization issues from the advanced integrated circuit manufacturing technologies lead to increase the probabilities of single node upset and multiple upsets errors of neighbor nodes. The study of such conjecture is mandatory to specify the protection requirements. This paper deals with the study of such single and multiple errors due to the impact of a single particle in the control unit...
The desirable use of Field-Programmable Gate Arrays (FPGAs) in aerospace & defense field has become a general consensus among IC and embedded system designers. Radiation-hardened (rad-hard) electronics used in this domain is regulated under severe and complex political and commercial treaties. In order to refrain from these undesired political and commercial barriers COTS FPGAs (despite the fact...
With NoCs (Networks-on-Chips) becoming a central part of today's many-core systems, ensuring a good level of performance at the routing level has never been so crucial. In previous works, we have introduced a novel method for designing fully adaptive deadlock-free routing algorithms for NoCs called ESPADA (EScape PAths with Dynamic channel Acquisition). The strength of our approach lies in its ability...
The power density of integrated circuits increases with the technology scaling, so the need of implementing low-power designs is increasing. The clock gating technique is typically employed to reduce the dynamic power consumption in digital integrated circuits. However, the use of this approach could affect the reliability of the device in the presence of soft errors caused by radiation. The objective...
In this work, a methodology to assess the implications on the performance of analog circuits due to the use of stacked devices in current nano-scale technologies is presented. To evaluate the usage of stacked devices, the characteristic curves of transistors implemented with a different amount of transistors in stack are obtained and compared to those of a single device. The effects of using stacked...
The improvement in Integrated Circuits density increases the fault occurrence probability. To ensure proper operation of critical systems, circuits testing becomes a task of extreme importance. Over the years, several methods have been proposed to optimize ATPGs (Automatic Test Pattern Generation). The optimization in test pattern generation aims to reduce the set of test vectors to be applied to...
To make a given circuit BIST-ready, unknown values appearing at the input of a MISR must be treated. In this paper, an LFSR-based X-masking circuit is employed and a method of seed generation for the LFSR to mask unknown values effectively is proposed. The seed generation method utilizes a stuck-at fault ATPG equipped with test pattern compaction. Experimental results for ITC'99 benchmark circuits...
This work presents a low cost automatic method to test vector generation for defect-oriented structural analog testing. An optimal set of analog single tone signals is obtained by computing the frequency response of circuit nodes, while iteratively injecting faults, using a SPICE simulator. The method also allows to identify the nodes of the circuit with higher observabilities to the injected faults,...
The stuck-at faults are basic faults that fail the chips. Various defects in the circuit can develop into stuck-at faults. To detect more defects caused by stuck-at faults, some of the fault sites may need to be detected multiple times. Thus, the existing pattern generation techniques provide N-detect ATPG, where each fault site would not be removed from the fault list before it is detected for N...
Network-on-Chip (NoC) is the most promising communication architecture for a scalable and high parallel System-on-Chip (SoC). Recent manufacturing technologies are very close to physical limitations increasing the number of faults during fabrication and operation; as a result, NoCs designed to be regular often will become irregular. Thus, the analysis of irregular topologies derived from regular ones...
In the last years, the phenomenon of electronic products passing all tests by the manufacturer but failing in the field (No Fault Found, or NFF) attracted the attention of industries and researchers. Delay faults are supposed to be among the contributors to this phenomenon. Hence, companies are increasingly adopting functional test as a final step, which is expected to detect this kind of defects...
With the ever increasing size of today's Very-Large-Scale-Integration (VLSI) designs new approaches for test pattern generation become more and more popular. One of the best known methods is SAT-based automatic test pattern generation (ATPG) which, in contrast to classical structural ATPG, first generates a mathematical representation of the problem in form of a Boolean formula. A specialized solver...
Selection of trace signals for an effective post-silicon validation and debug process is a challenging problem. State restoration has been widely used as a metric for the identification of trace signals. This paper presents a topology based methodology for selecting trace signals such that the error detection latency is minimized. The proposed methodology assists in selecting trace signals capable...
With the increasing adoption of embedded systems in critical automotive applications, the verification of hardware designs reliability is becoming a strictly regulated process where the ISO26262 standard plays a key role. Today crucial verification activities such as failure analysis and FMEA are still relying heavily on reliability engineer expertise, as automatic methods supporting them are still...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.