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In this paper, a layout design of an accurate Metal-insulator-Metal (MIM) capacitor array for reducing parasitic influences is presented. Parasitic capacitance due to interconnecting wires is well-matched. Parasitic resistance can be reduced for less routing track used. Post layout simulation results show that percentage errors of capacitor ratios are generally 0.02% A 16-bit analog-to-digital converter...
Radiation effects in ICs have been a hot topic in the reliability area for a long time. In the sub-lOOnm process technology, the Single-Event Effect (SEE) becomes most critical, and the modeling of Single-Event pulse is an important and challenging issue. In this paper a compact model of Single-Event pulse has been developed with VerilogA behavioral language. This model has also been used for the...
In this paper, a 12 bit 500MS/s SHA-less ADC is described. The ADC has an integrated input buffer with a new linearization technique that improves its distortion. Eight pipeline stages with fully differential switched capacitor architecture follow the input buffer. Each of stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage...
We have developed a radiation-hardened standard cell library for space applications based on the commercial 65nm CMOS technology process. The standard cells are designed using some radiation-hardened (RH) techniques, and the effects of these RH approaches have been validated. Also this 65nm CMOS RH standard cell library has been characterized to support the verilog to GDSII design flow, and the designed...
The high-performance standard cell library is very important for the ASIC design. A radiation-hardened standard cell library can significantly enhance the reliability and performance of digital circuits that work in a hard radiation environment. We have developed a radiation-hardened standard cell library for the commercial 0.18µm CMOS technology. Some of the radiation-hardened techniques (such as...
This paper presents a low power 14-bit 500 MS/s analog-to-digital converter (ADC) in 180 nm CMOS process. By interleaving two 250 MS/s pipelined sub-ADC on a single chip, an aggregate sample rate of 500 MS/s is achieved. Background calibration techniques are used for offset mismatch, gain mismatch, and phase mismatch calibration between time-interleaved sub-ADC channels. An analog delay cell is utilized...
The radiation-hardened standard cell library can greatly improve the life-time and reliability of ASICs used in space applications. In this paper, we have discussed several radiation-hardened techniques, and have used SPICE simulation to validate these approaches. Finally, using these RH techniques, we have developed a radiation-hardened standard cell library based on 0.18 µm CMOS technology.
In this paper, a high-speed front-end circuit used in a pipeline analog-to-digital (ADC) is described. Time constant matching of the sampling networks, feedback factor of the amplifier, implementation of double duty cycle DCS (duty cycle stabilizer), and using of the reference are discussed. The high-speed front-end circuit design technique is applied to a 16-bit 250MSPS pipeline ADC. Simulation confirms...
When DAC is applied to communication field, it is generally necessary to have a good dynamic performance. However, nonlinear distortion of output stage current switch has a potent effect on DAC as a whole. The approach proposed in this paper aims to improve on distortion in output stage. As a result of practical measurement, clock frequency is 200MHz, and SFDR of the DAC with a data frequency of 20MHz...
Output setting time of operational amplifier consists of output large-signal setting time and output small-signal setting time. In order to increase the output setting time, it is necessary to increase both the slew rate and the gain-bandwidth product at the same time. In this paper, an operational amplifier structure is designed which can increase SR and GBW. The GBW of the whole operational amplifier...
The requirements of segmented current-steering DAC's MSB part for transistor matching are very high. In this paper, a diagonal layout is presented which can meet very well the requirements of 12-bit DAC monotonicity. The DAC was developed in TSMC 0.18um process technology. As a result of measurements, the static errors are: DNL=±0.15LSB, and INL=±0.2LSB.
A simple low power current sensor for DC-DC converters is presented in this paper. The proposed current sensor is designed without using amplifier. This greatly reduces the power consumption and significantly saves silicon area. Simulation shows less than 20uA total current consumption can be achieved by using this structure. The performance of this design is robust to temperature variations. The...
In this paper, a high-speed direct digital frequency synthesizer digital circuit design is presented, which integrates phase accumulator, phase offset producer, sine/cosine mapping function, amplitude modulator, clock generator. The DDFS is processed in 0.18 ??m TSMC CMOS technology. The verification results show that the DDFS capable of handling frequency, phase, amplitude modulation and generating...
In this paper, an ultra-high-speed, differential current-steering mode 10-bit D/A converter is presented. The converter consists of 8-channel time division multiplexer, 5-31 ??thermometer?? decoder, fast current conversion switch, constant current source array, and other units, is processed in 0.35 ??m SiGe BiCMOS standard process technology, and has a data fresh rate of up to 1 GSPS. First, the circuit...
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