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The evolution of silicon and silicon-germanium pnp transistors is reviewed in this paper. The motivation for SiGe-pnp transistors in Complementary Bipolar (CBi) and CBiCMOS is discussed with a view on device parametric parameters that help gage the usefulness of these devices in analog and RF design. We review the basic process architectures and process building blocks for CBiCMOS. SiGe-pnp versus...
A physics-based silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) aging model for mixed-mode stress based on the lucky-electron model and reaction-diffusion theory is developed for integration with compact models. An effective aging parameter extraction method is described, and the aging model parameters are fit for a modern SiGe HBT platform. The aging model is implemented as a wrapper...
An empirical reliability model is proposed here that is able to predict parameter degradation for a SiGe Hetero-junction Bipolar Transistor (HBT) by scaling stress time laterally producing a universal curve that describes whole time evolution of degradation. The predictability of the degradation pattern is demonstrated in experiments at a forward active mode as well as the reverse Veb stress accounting...
We present in this work the impact of electrical reliability stress on low-frequency noise for SiGe HBTs in forward and inverse modes. The reverse EB stress and the forward mixed-mode stress are investigated. For the first time inverse mode noise is used as a tool to investigate stress-induced damage. The fact that reverse EB stress degrades SiGe HBTs low-frequency noise in the forward mode but not...
Contact Electromigration (EM) constraining the performance for a SiGe hetero-junction bipolar transistor (HBT) is investigated. By incorporating a stacked contact structure with Via, the time-to-fail (TTF) increases by ten-fold and contact EM current density (JC_CNT_EM) increases by three-fold. These improvements are shown in experiments incorporating a space between contact and Via, a multi-level...
The implementation of safe operating area (SOA) is discussed in this paper to quantify electrical, thermal, and Hot Carrier (HC) limits for a SiGe hetero-junction bipolar transistor (HBT) in a forward active mode. An electrical limit should be constructed to prevent an unexpected catastrophic failure at a circuit level considering impedance to the base node of HBTs simultaneously affected by current...
The equation of resistance drift governing oxidation is derived in this paper for Copper-Top (Cu-Top) interconnects to assess reliability of Cu-Top. Our equation is not only demonstrated by thermal storage tests at various temperatures but also characterized by dependence of time, temperature, metal width, and additional dielectric & conductive layers over Cu-Top. As a result, this approach enables...
The RF linearity characteristics of complementary (npn + pnp) SiGe HBTs are investigated with respect to bias and frequency dependence, for the first time. The differences in distortion performance between npn and pnp SiGe HBTs are examined. Overall, at low bias currents (e.g., for minimum RF noise), both devices exhibit similar linearity performance and power gain, while for higher bias currents...
The RF safe-operating-area of a variety of both bulk and thick-film SOI SiGe HBTs SiGe has been investigated using DC and pulsed-mode output characteristics, as well as RF gain and linearity measurements. SOI SiGe HBTs are found to suffer more from self-heating than bulk devices under DC operating conditions, as expected, due to their naturally higher thermal resistance. However, in terms of RF performance,...
Footprint design in SiGe BiCMOS SOI technology is described in this paper to improve device performance matrix. The safe operating area (SOA) for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) is significantly improved as the footprint area increases. The Early voltage for SiGe HBT on SOI at medium-high bias range also increases substantially with footprint...
A unified electro-thermal safe operating area (SOA) expression is proposed in this paper to evaluate self heating, impact ionization, and hot carrier (HC) degradation effects simultaneously in a full range of bipolar transistor operation. This SOA is demonstrated by experiments for a SiGe hetero-junction bipolar transistor (HBT) fabricated on silicon on insulator (SOI) by extracting principle parameters...
Unique analog product application requirements such as high speed, low noise, low power, high precision and high voltage demand complex analog process technologies. This complexity poses several reliability challenges that are specific to each technology. In this paper some of the key reliability mechanisms in most common analog process technologies are highlighted. To meet broad range of analog IC...
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