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Thermal compression bonding (TCB) is becoming an increasingly important process step in the assembly of advanced components such as fine pitch flip chip packages, system-in-package products, and 3D IC's. To increase the throughput and robustness of TCB processes, it is crucial to understand and control important process parameters like time, force and temperature. However, for TCB processes it becomes...
Processing of bump-less or embedded microbumps is introduced in this paper as an approach which enables scaling microbumps for below 10um pitches. Landing wafer is standard damascene process and in top wafer bumps are embedded in a soft backed polymer. Later during thermo-compression bonding this polymer is cured to bond two chips together. Process flow and results of TC bonding is discussed in this...
A feasibility study of die-to-wafer (D2W) bonding of inorganic dielectric layers is conducted on common industrial tools in a typical cleanroom environment. With the help of an additional cleaning step after dicing of the top wafers or using stealth dicing process, 100% bonding success rate from wafers with chemical mechanical polished (CMP-ed) SiO2 has been achieved. Plasma treatment of the top dies...
We investigate multi-stack dielectric wafer bonding through two integration schemes, which provide different paths to realize vertical integration of multiple device layers. Key process steps are evaluated and optimized to enable void-less bonds at different bonding layers. Meanwhile, issues related to the wafer edge are discovered during the backside processing and the impact is analyzed. Finally,...
In this paper a bump-less process is introduced in order to further scale down the pitch of microbumps. Electrical resistance measurement, Cross section SEM and mechanical characterizations show successful 3D stacking using proposed method.
Thermal compression bonding (TCB) process in combination with a pre-applied underfill material has been developed and investigated for assembling 20 μm pitch Sn-based micro bumps. It is found bonding force has a profound impact on the joint formation behavior. A low bonding force produces bump joints with heavier underfill entrapment and incompletely reacted solder. A higher bonding force leads to...
3D stacked IC (SIC) vs. 3D Interposer wafer processing and assembly challenges are discussed in this paper. We report on the key enabling technologies like wafer thinning, thin wafer handling, TSV, micro bumping, package bumping, stacking and packaging. The limited micro bump yield loss in the 3D SIC case is explained by modeling of bonding force distribution. It is also shown that for sequential...
Assembling multi-layer thinned Si chips to form 3D ICs in a fast, reliable, and cost-effective manner is one of the key processes to enable wider application and commercialization of 3D integration. In this paper the essential aspects of process development for stacking multi-layer 3D ICs are investigated. Combining thermo-compression bonding (TCB) process and the usage of pre-applied wafer-level...
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