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The Cutting edge Reconfigurable ICs for Stream Processing (CRISP) project aims to create a highly scalable and dependable reconfigurable system concept for a wide range of tomorrow’s streaming DSP applications. Within CRISP, a network-on-chip based many-core stream processor with dependability infrastructure and run-time resource management is devised, implemented, and manufactured to demonstrate...
In this paper, functional unit-based IDDT testing has been applied for a 90nm VLIW processor to monitor its aging degradation. This technique can provide health data for reliability evaluation as used in e.g. prognostic software for lifetime prediction. The test-program development based on the architecture of a single DSP processor, as well as implementation of an accelerated test (AT) is investigated...
In avionics, like glide computers, the problem of No Faults Found (NFF) is a very serious and extremely costly affair. The rare occurrences and short bursts of these faults are the most difficult ones to detect and diagnose in the testing arena. Several techniques are now being developed in ICs by us to cope with one particular category of NFFs, being the intermittent resistive faults (IRF). The reuse...
Anisotropic Magnetoresistance angle sensors are widely used in automotive applications considered to be safety-critical applications. Therefore dependability is an important requirement and fault-tolerant strategies must be used to guarantee the correct operation of the sensors even in case of failures. AMR sensors are configured with two Wheatstones bridges where catastrophic (hard) as well as parametric...
Usually Anisotropic Magnetoresistance angle sensors are configured with two Wheatstone bridges, but an undesirable offset voltage included in the sensor output affects its accuracy. The total offset voltage combines a voltage due to resistance mismatches during manufacturing and a voltage from inequalities in the magnetic sensitivity. This paper focuses on identifying a consistent trend between the...
Successive-approximation-register (SAR) analog-to-digital converters (ADCs) represent the majority of the ADC market from medium to high resolution ADCs. Due to its low power, high-performance and small area in Mega-Hz range, SAR ADCs are increasingly attractive for todays safe-critical applications like automotive. Recently, much research has been carried out on self-calibrations of SAR ADCs, which...
The idea of an embedded instrument (EI) is to embed some form of test and measurement into silicon to characterize, debug and test chips. The concept of the EI is different from build-in self test (BIST) and other kinds of monitors by the fact that embedded instruments can provide the user with rich and detailed information with respect to the performances of the target, not just a true/false indication...
The offset voltage is an undesirable voltage included at the output of an anisotropic magnetoresistance angle sensor, which affects the accuracy of the angle measurement. This voltage changes with sensor aging and hence should be compensated not just at the moment of manufacturing but also during the sensor lifetime. This can be accomplished by an online offset voltage compensation method. However,...
Traditional reliability tests use complicated equipment, like probe stations and semiconductor parameter analyzers, to measure changes in transistors' threshold voltages, which are both expensive and time consuming. This paper provides an idea to test the threshold voltage with existing low-to-moderate accuracy ADCs and DACs inside SoCs. To avoid the low-accuracy limitation of measurement results,...
A major threat in extremely dependable high-end process node integrated systems in e.g. Avionics are no failures found (NFF). One category of NFFs is the intermittent resistive fault, often originating from bad (e.g. Via or TSV-based) interconnections. This paper will show the impact of these faults on the behavior of a digital CMOS circuit via simulation. As the occurrence rate of this kind of defects...
In this paper, functional IDDQ testing has been applied for a 90nm VLIW processor to effectively detect aging degradation. This technique can provide health data for reliability evaluation as used in e.g. prognostic software for lifetime prediction. The test environment for validation, implementing an accelerated test (AT), has been investigated and IDDQ measurement data resulting from AT is presented...
A significant portion of mixed-signal integrated systems is already used in safety-critical applications, such as transportation. It has often to operate under harsh environmental conditions for a long time (aging). One example is car electronics for the future generation of drive-by-wire. As a result the electronics used here has to be resilient for aging.
Embedded instruments are becoming used more often in modern SoCs for different testing and measurement purposes. IEEE 1687 (iJTAG) is a newly IEEE approved draft standard for embedded instruments access and control based on the widespread IEEE 1149.1 TAP port. In this paper the work done for enabling iJTAG control, observation and reconfiguration of complex digital embedded instruments will be discussed...
The most difficult fault category in electronic systems is the “No Fault Found” (NFF). It is considered to be the most costly fault category in, for instance, avionics. The relatively few papers in this area rarely deal with analogue integrated systems. In this paper a simple simulation model has been developed for a particular type of NFF, the intermittent resistive fault resulting from bad interconnections...
An embedded health-monitoring infrastructure for a highly reliable MP-SoC for data-streaming systems is presented. Different from the traditional approach of a dependable design, our infrastructure is based on life-time prognostics from health-monitoring sensors that are embedded near the target processor. This enables the preventive repair by spare parts or priority ranking of tasks among processors...
A new generation of highly dependable multi-processor Systems-on-Chip for safety-critical applications under harsh environments with zero down-time is emerging. In this paper1, the approach towards reaching this ultimate goal is explained. Crucial is this method is linking the measurement data of so-called (on-chip) health monitors during life time with the measurements of degrading key performance...
This paper presents two soft-error mitigation methods for DSP processors. Considering that a DSP processor is composed of several functional units and each functional unit constitutes of a control unit, some registers and combinational logic, a unique characteristic of DSP workloads has been deployed to develop a masking mechanism for the control-logic of each functional unit. Combinational logic...
In this paper, system-level behavioural models are used to simulate the aging-related degradation effects in the DAC capacitor array of a charge-redistribution successive approximation register (SAR) ADC because of the large calculation time of transistor-level aging simulators. A performance-analysis system based on the degraded models has been implemented in the LabVIEW environment in order to study...
Analog and mixed-signal IPs are increasingly required to use digital fabrication technologies and are deeply embedded into system-on-chips (SoC). These developments append more requirements and challenges on analog testing methodologies. Traditional analog testing methods suffer from less accessibility and control with regard to these embedded analog circuits in SoCs. As an alternative, an embedded...
Aging-sensitive technology nodes that are resulting in performance degradations in their electronic system implementations require aging simulations in advance for a more dependable design. Simulating time-domain aging effects in these electronic systems, especially in complex analog and mixed-signal systems like analog-to-digital converters, are time consuming and is often impossible for larger designs...
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