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Conference proceedings front matter may contain various advertisements, welcome messages, committee or program information, and other miscellaneous conference information. This may in some cases also include the cover art, table of contents, copyright statements, title-page or half title-pages, blank pages, venue maps or other general information relating to the conference that was part of the original...
The progressive shrinking of device size in advanced technologies leads to miniaturization and performance improvements. However, ultra-deep sub-micron technologies are more vulnerable to soft errors. Error analysis of a complex system with a sufficiently large sample of vulnerable nodes takes a large amount of time. In this paper we propose RASVAS, a hierarchical statistical method to model, analyze,...
Analyzing the impact of software execution on the reliability of a complex digital system is an increasing challenging task. Current approaches mainly rely on time consuming fault injections experiments that prevent their usage in the early stage of the design process, when fast estimations are required in order to take design decisions. To cope with these limitations, this paper proposes a statistical...
Laser fault injection into SRAM cells is a widely used technique to perform fault attacks. In previous works, Roscian and Sarafianos studied the relations between the layout of the cell, its different laser-sensitive areas and their associated fault model using 50 ns duration laser pulses. In this paper, we report similar experiments carried out using shorter laser pulses (30 ps duration instead of...
For many applications, reliability, availability and trustability are key factors, requiring careful design to meet the end users expectations. The complex ASICs, which are now ubiquitous, often embed tens of millions of flip-flops, hundreds of megabits of embedded SRAM, and hundreds of millions of combinatorial cells. These designs integrate IP from multiple providers and are implemented in advanced...
This paper presents an accurate soft error propagation analysis technique for processor SER evaluation. Especially, we focus on Single Event Upset (SEU) in flip-flop which is a main contributor of processor SER. SEUs in flip-flops propagate combinational circuits with temporal masking and logical masking effects. The temporal masking is disabled when the erroneous flip-flop is disabled. The proposed...
The paper proposes a novel hybrid architecture to consolidate avionic applications with different levels of criticality in a multicore processor. The architecture stems from the need of deploying into one computer different applications with conflicting requirements in terms of criticalities that today are mapped into multiple independent computers. The architecture relies on a type-1 hypervisor to...
The case of a defected TSV that has been cracked at the point where an impurity or a void hole originally had been is analyzed in this study. A lumped analytical electrical circuit that models the behavior of this defect is proposed. TSV fault modeling offers assistance in developing new test methods that would improve the reliability of the 3D ICs. The structure is simulated using a commercial 3D...
This paper proposes a method to select a set of paths representative of the behavior of a processor under NBTI conditions. The selected paths are the ones that are expected to fail first due to aging for any executed application.
Recently, several application areas in the test domain (e.g., burn-in and aging monitoring) started to require suitable input stimuli, able to maximize the switching activity of a certain module for a certain period of time. If the module is part of a processor, this turns into identifying a suitable sequence of instructions, able to maximize the switching activity. This paper proposes a method to...
This paper presents a new and highly efficient approach for the estimation by fault injection of the sensitivity to Single Event Upsets of circuits implemented in Xilinx SRAM-based FPGAs. The proposed approach prioritizes fault injection in specific configuration bits subsets defined according to their contents and the type of FPGA resources that they are configuring. The new approach also allows...
In this paper, we analyze the vulnerability of Salsa20 stream cipher against power analysis attacks, especially against correlation power analysis (CPA), which is the strongest form of power analysis attacks. In recent literature, a rigorous study of optimal differential characteristics is presented, but an analysis of the resistance of the cipher against power analysis side-channel attacks remains...
Fully delay testable circuits obtained by covering ROBDD nodes with Invert-AND-OR sub-circuits and Invert-AND-XOR sub-circuits implementing Shannon decomposition formula are considered. Algorithms of finding test pairs for robust testable PDFs and validatable non robust testable PDFs of resulted circuits have been developed. They have a polynomial complexity. Experimental results demonstrate essential...
The susceptibility of memory elements (latches, flip-flops) to soft errors is increased as CMOS technology scales down, due to multi-node charge collection by the impact of energetic particles on silicon. Existing design solutions provide partial or no immunity to SEUs that affect a pair of nodes. In this work, we propose a new latch topology, which provides complete protection from SEU related double...
An approach for Trojan circuit detection in a finite state machine is presented. It is based on a model where long sequences of inputs that are applied to the system in the functional mode can detect if Trojan hardware is triggered with high probability. An efficient and scalable input generation algorithm for broadside tests is introduced.
Soft errors due to alpha particles, neutrons and environmental noise are of increasing concern due to aggressive technology scaling. While prior work has focused mostly on error resilience of linear signal processing algorithms, there is increasing need to address the same for nonlinear systems used in emerging applications for sensing and control. In this paper, a new approach for detecting errors...
Most of Wireless Sensor Networks are deployed to monitor a set of targets over a specified area. The lifetime of such a network is defined as the time duration from the network deployment till the time when one target is no longer covered. Thus, this lifetime is limited by the energy resource of sensor nodes. In order to maximize the lifetime of the network, only a subset of nodes capable of covering...
Anisotropic Magnetoresistance angle sensors are widely used in automotive applications considered to be safety-critical applications. Therefore dependability is an important requirement and fault-tolerant strategies must be used to guarantee the correct operation of the sensors even in case of failures. AMR sensors are configured with two Wheatstones bridges where catastrophic (hard) as well as parametric...
NoCs (Networks-on-Chip) are an attractive alternative to communication buses for SoCs (Systems-on-Chip) as they offer both high scalability and low power consumption. However, designing such systems in the nanoscale era brings up some serious concerns about reliability. Our aim is to design robust NoCs while limiting performance degradation. In this paper, we introduce several techniques meant to...
Networks-on-Chip (NoC) have been established as the de facto standard for on-chip communication in multi-/many-core systems, due to their innate scalability properties pertaining to performance and physical implementation. Spanning the entire chip, the NoC suffers from both inter-die and intra-die variations. In addition to static variability, the NoC is also afflected by dynamic variations, such...
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