The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In-field on-line testing techniques have recently been proposed for permanent fault detection caused by wear-out/aging-related defects manifesting during the lifetime of a system. Selective Software-Based Self-Testing (SBST) is one such paradigm focusing primarily on the recently stressed functional units of a multicore system at a sub-core granularity, in an attempt to reduce the application performance...
Design debugging poses a major bottleneck in modern VLSI CAD flows, consuming up to 60% of the verification cycle. The debug pain, however, worsens in regression verification flows at the pre-silicon stage where myriads of failures can be exposed. These failures need to be properly grouped and distributed among engineers for further analysis before the next regression run commences. This high-level...
With VLSI scaling, “no trouble found” or NTF field returns have increased due to the dominance of soft defects over hard defects. An analysis of networking and DSP NTF field returns shows outlying behavior in not only product parameters but also on-die process parameters revealing new mitigation opportunities. The resulting yield hit is demonstrated to be minor <0.5% to catch NTFs that can be >50%...
We illustrate that memory repair for high fault rates can be exploited for improving yield, extending lifetime, reducing power, and improving reliability, and consequently can be used to push aggressively the limits of technology scaling. We also present recent advances in low-area and low-power memory repair for high fault rates. As one of our main goals is to use this repair for reducing as much...
Anisotropic Magnetoresistance angle sensors are widely used in automotive applications considered to be safety-critical applications. Therefore dependability is an important requirement and fault-tolerant strategies must be used to guarantee the correct operation of the sensors even in case of failures. AMR sensors are configured with two Wheatstones bridges where catastrophic (hard) as well as parametric...
Most of Wireless Sensor Networks are deployed to monitor a set of targets over a specified area. The lifetime of such a network is defined as the time duration from the network deployment till the time when one target is no longer covered. Thus, this lifetime is limited by the energy resource of sensor nodes. In order to maximize the lifetime of the network, only a subset of nodes capable of covering...
Algorithms are proposed to diagnose defects in a defect tolerant field programmable interconnection network embedded in a large area integrated circuit. The proposed diagnosis algorithms use a diagonal configuration approach to reduce the cone of influence of individual tests, thus allowing parallel tests according to diagonal patterns. The proposed algorithms avoid redundant diagnosis tests. Efficiency...
NoCs (Networks-on-Chip) are an attractive alternative to communication buses for SoCs (Systems-on-Chip) as they offer both high scalability and low power consumption. However, designing such systems in the nanoscale era brings up some serious concerns about reliability. Our aim is to design robust NoCs while limiting performance degradation. In this paper, we introduce several techniques meant to...
Networks-on-Chip (NoC) have been established as the de facto standard for on-chip communication in multi-/many-core systems, due to their innate scalability properties pertaining to performance and physical implementation. Spanning the entire chip, the NoC suffers from both inter-die and intra-die variations. In addition to static variability, the NoC is also afflected by dynamic variations, such...
The progressive shrinking of device size in advanced technologies leads to miniaturization and performance improvements. However, ultra-deep sub-micron technologies are more vulnerable to soft errors. Error analysis of a complex system with a sufficiently large sample of vulnerable nodes takes a large amount of time. In this paper we propose RASVAS, a hierarchical statistical method to model, analyze,...
In this paper we propose a leakage-aware soft error tolerant storage element, implementable in standard CMOS technology and able to operate both as a CAM and as a TCAM cell. The proposed cell is immune to SNUs (Single Node Upsets) when operating as a CAM cell and demonstrates partial resilience (75%) when operating as a TCAM cell. Simulation results in SPICE at a 45nm PTM technology show a significant...
A new roll-forward technique is proposed that recovers from any single fail-stop failure in M integer data streams (M ≥ 3) when undergoing linear, sesquilinear or bijective (LSB) operations, such as: scaling, additions/subtractions, inner or outer vector products and permutations. In the proposed approach, the M input integer data streams are linearly superimposed to form M numerically entangled integer...
Linear system solvers are key components of many scientific applications and they can benefit significantly from modern heterogeneous computer architectures. However, such nano-scaled CMOS devices face an increasing number of reliability threats, which make the integration of fault tolerance mandatory.
We propose a novel dynamic voltage scaling (DVS) approach for reliable and energy efficient cache memories. First, we demonstrate that, as memories age, leakage power reduction techniques become more effective due to sub-threshold current reduction with aging. Then, we provide an analytical model and a design exploration framework to evaluate trade-offs between leakage power and reliability, and propose...
The Physical Unclonable Function (PUF) has broad application prospects in the field of hardware security. The arbiter PUF is a typical kind of strong PUF. However, due to its deterministic logic, attackers can use modeling techniques to break it in short time. Therefore, this paper proposes an Obfuscation logic based PUF (OPUF) design. A Boolean obfuscation module is proposed to obfuscate the logic...
Bulk Built-In Current Sensors (BBICS) were developed to detect the transient bulk currents induced in the bulk of integrated circuits when hit by ionizing particles or pulsed laser. This paper reports the experimental evaluation of a complete BBICS architecture, designed to simultaneously monitor PMOS and NMOS transistors, under Photoelectric Laser Stimulation (PLS). The obtained results are the first...
Fault-tolerant architectures have been widely used in industry to prevent circuit reliability from becoming a bottleneck for the development of robust high-performance and low-power systems. One such solution is a Hybrid Fault-Tolerant Architecture that offers benefits such as low power and lifetime reliability improvement. However, it has been identified that there is room of improvement in efficiency...
The susceptibility of memory elements (latches, flip-flops) to soft errors is increased as CMOS technology scales down, due to multi-node charge collection by the impact of energetic particles on silicon. Existing design solutions provide partial or no immunity to SEUs that affect a pair of nodes. In this work, we propose a new latch topology, which provides complete protection from SEU related double...
Soft errors due to alpha particles, neutrons and environmental noise are of increasing concern due to aggressive technology scaling. While prior work has focused mostly on error resilience of linear signal processing algorithms, there is increasing need to address the same for nonlinear systems used in emerging applications for sensing and control. In this paper, a new approach for detecting errors...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.