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An earlier paper showed that the accuracy of a fault diagnosis procedure based on single faults is reduced when it attempts to diagnose transition faults that are clustered in an area. This is due to the increased possibility that the effects of clustered faults will interact. This paper defines three different types of clusters. In path-based clusters, transition faults are clustered along a subpath...
This work considers the use of a mixed structural-functional approach to path delay fault test generation and compaction. K Longest Paths per Gate (KLPG) are generated using structural information and filtered using direct implications and heuristics. These paths are then justified using Boolean satisfiability (SAT) algorithms. The paths are dynamically compacted into test patterns, using structural...
This paper presents a novel approach to functional fault diagnosis adopting data mining to exploit knowledge extracted from the system model. Such knowledge puts into relation test outcomes with components failures, to define an incremental strategy for identifying the candidate faulty component. The diagnosis procedure is built upon a set of sorted, possibly approximate, rules that specify given...
Millimeter-wave (mm-wave) wireless interconnects have emerged as a promising solution to the energy-latency issues of global interconnects. Wireless Network-on-Chip (WiNoC) architectures with CMOS compatible mm-wave transceivers can achieve significant improvements in performance and energy-efficiency in on-chip data transfer for multicore chips. A token-based medium access mechanism is used in several...
The incorporation of error detection and recovery mechanisms becomes mandatory as the probability of the occurrence of transient faults increases. The detection of control flow errors has been extensively investigated in literature. However, only few works have been conducted towards recovery from control-flow errors. Generally, a program is re-executed after error detection. Although re-execution...
In highly scaled nano-CMOS devices, soft errors and aging defects are a design concern. Online detection of errors is necessary to address such errors. For online error detection in microprocessors, redundant execution of the entire pipeline has been studied. Software solutions for such re-execution impose significant performance penalty due to competition for execution resources between the main...
This paper presents a novel method for synthesizing fault-secure circuits based on parity codes over groups of circuit outputs. The fault-secure circuit is able to detect all errors resulting from combinational and transition faults at a single node. The original circuit is not modified. If the original circuit is non-redundant, the result is a totally self-checking circuit. At first, the method creates...
As technology scales deep into the sub-micron regime, transistors become less reliable. Future systems are widely predicted to suffer from considerable aging and wear-out effects. This ominous threat has urged system designers to develop effective run-time testing methodologies that can monitor and assess the system's health. In this work, we investigate the potential of online software-based functional...
This paper presents a concurrent error detection (CED) scheme for Orthogonal Latin Square (OLS) parallel decoders. Different from a CED scheme found in the technical literature that protects only the syndrome generator, the proposed CED scheme protects the whole OLS decoder for single stuck-at faults. This paper presents the detailed design and analysis of the proposed CED scheme and shows that it...
This paper presents a run-time resource manager for NoC-based many-core architectures that dynamically determines the most effective mapping of tasks on the processing nodes of the architecture to optimize system reliability while leveraging on performance and communication energy. An adaptive engine is exploited to pursue the given optimization goal taking into account various metrics. Experimental...
Aging-sensitive technology nodes that are resulting in performance degradations in their electronic system implementations require aging simulations in advance for a more dependable design. Simulating time-domain aging effects in these electronic systems, especially in complex analog and mixed-signal systems like analog-to-digital converters, are time consuming and is often impossible for larger designs...
This paper describes a cross-layer design method for digital circuit fault-tolerant design. This cross-layer hierarchical scheme mainly contains selective duplication in logic level and spare cache design in micro-architecture level, working together seamlessly. When compared to traditional fault tolerance techniques, this method takes advantage of information from different circuit design levels...
Due to scalability issues of existing semiconductor memories emerging non-volatile memory technologies are gaining increasing interest. Their promising features like non-volatility, low-power consumption, and great scalability are expected to meet demands of upcoming digital systems. Unfortunately, due to their characteristics they often require special management. Moreover, due to certain properties,...
Variability analysis of nanoscale transistors and circuits is emerging as a necessity at advanced technology nodes. Technology Computer Aided Design (TCAD) tools are powerful ways to get an accurate insight of Process Variations (PV). However, obtaining both fast and accurate device simulations is impractical with current TCAD solvers. In this paper, we propose an automated output prediction method...
A new clocked design that uses memristors in current mode logic implementation of threshold logic gates is presented. Memristor based designs have high potential to improve performance and energy over purely CMOS-based current mode logic implementations. The proposed design is clocked, and outperforms a recently proposed combinational method in performance as well as energy consumption. A fault tolerant...
Various emerging technologies promise advantages with respect to integration density, performance or power consumption, at the cost of approximate or probabilistic behavior. Approximate computing, where limited computational inaccuracies are tolerated at the system or application level is therefore of increasing interest. This paper investigates the use of stochastic computing (SC) as a tool for approximate...
Outsourcing of the various aspects of IC design and fabrication flow strongly questions the classic assumption that “hardware is trustworthy”. Multiprocessor System-on-Chip (MPSoC) platforms face some of the most demanding security concerns, as they process, store, and communicate sensitive information using third-party intellectual property (3PIP) cores that may be untrustworthy. The complexity of...
This paper introduces a novel design for a multiple node upset tolerant flip-flop. This design uses the TDICE memory cell that was proposed in the technical literature for memory arrays and applies its principles of operation to a Master Slave flip-flop implemented at 65 nm CMOS technology. It is shown that the proposed design approach is particularly suited for flip-flops targeting highly radioactive...
Defects as well as soft errors are a growing concern in micro and nanoelectronics. Multiple faults induced by single event effects are expected to be seen more often. Thus, reliability has become an important design criterion. In this context, we are concerned about the susceptibility of SRAM-based FPGA's logic blocks to multiple single event transients. Our target is to select the most reliable CLB...
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