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An adaptive region-of-interest panoramic system is firstly proposed to achieve high-quality and real-time processing for 360-degree panorama. This technique prevents from processing a whole 360-degree image by only focusing on the particular area. Several memory optimizing methods, including cache-miss rate and memory buffer size reduction, are also applied with the purpose of improving the run time...
A 4K×2K video processor supporting 360-degree processing over the smart-phone is first-reported. Two 182° fisheye cameras are exploited to warp and blend the circle video into a 4K panorama one. Fast blending architecture reused the memory buffer and reduce the unused operating area while keep high blending quality, and therefore achieve 4K 360-degree, equivalently 1K 90-degree video processing over...
A lower power and area efficient VP9 and multi-standard video decoder chip is first-reported for Android 4K TV. It supports prevalent MPEG-x, VP-x, RMx, WMV-x and H.26x series video standards in a single chip. Three high-throughput techniques, look-ahead re-mapping, early stage pipeline and dynamic-scheduled bus translation, are proposed. They cuts the processing times by 51.2% compared to the state-of-the-art...
A 4K×2K video processor supporting 360-degree video recording over the smart-phone is first-reported. Two 180° fisheye cameras are exploited to stitch the circle video into a panorama one. Fast stitching algorithms reused the neighboring pixel and reduce the unused operating area while keep high stitching quality, and therefore achieve 4K real-time recording over 2.5GHz octa-core ARM CPU and Power...
A 4 K 2 K H.265/HEVC video codec chip supporting 14 video standard formats is implemented on a 1.491.45 mm die in a 28 nm CMOS process. Several HEVC fast algorithms reduce the coding modes by analyzing the content features leading to over 68.5% and 83% of complexity reduction in intra and inter coding, respectively. A fully parallel processing element (PE) array is adopted...
Multi-frame super-resolution performance would highly depends on the quality of low-resolution observations. While a wide range of multi-frame super-resolution algorithms now exist, the selection design of low resolution images has not been adequately explored. This paper presents an OpenCV-based multi-frame super resolution and explores a sharpness index to optimize the low-resolution images. The...
A 4K and Main-10 HEVC video decoder LSI is fabricated in a 28nm CMOS process. It adopts a block-concealed processor (BcP) to improve the visual quality and a bandwidth-suppressed processor (BsP) is newly designed to reduce 30% and 45% of external data accesses in playback and gaming scenario, respectively. It features fully core scalable (FCS) architecture which lowers the required working frequency...
A 4K×2K H.265/HEVC video codec chip is fabricated in a 28nm CMOS process with a core area of 2.16mm2. This LSI chip integrates a dual-standard (H.265 and H.264) video codec and a series of prevalent (VC-1, WMV-7/8/9, VP-6/8, AVS, RM-8/9/10, MPEG-2/4) decoders into a single chip. It contains 3,558K logic gates and 308KB of internal SRAM. Moreover, it simplifies intra/inter-rate-distortion optimization...
A first-reported 4K×2K@60fps and Main-10 HEVC video decoder integrating 14 video formats is fabricated in a 28nm CMOS process. It adopts an Adaptive Coding Unit Balance (ACUB) and Data-Sharing Wave-front Dual-core (DSWD) architectures to lower the required working frequency by 65%. A 10-bit Smart Pixel Storage (SPS) scheme is proposed to reduce the frame buffer space by 37.5%. Moreover, a weighted...
This paper presents a panoramic video system by direct manipulation video navigation without any image stitching. Our panoramic video browsing is interacted with user by displaying overlapped region of consecutive input video frames with corresponding viewing angle. That is, when user slides, the panoramic video will switch video frames to corresponding viewing angle according to sliding distance...
A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression...
A first dual-standard video encoder and decoder LSI providing VP8 (i.e. video format of WebM project for use of web's video) or H.264/AVC video recording and playback simultaneously is implemented with 28nm CMOS and occupies 1.94mm2 of core area. Several area-efficient techniques are realized, leading to 43.6% of area reduction. A new rate control is designed to facilitate the adaptation of video...
Multi-core platform has become a trend in hand-held embedded systems, such as smartphone and tablet. To improve the video decoding performance by using the multiple cores, one of parallel algorithms should be adopted. However, different parallel algorithm should be selected for different video standard on different platform. Therefore, an engine to estimate performance on a target platform from existing...
a 3D Blu-ray-compliant multimedia processor integrating video decoder, display and graphic engines is presented. To cope with the bandwidth/cost-starved Blu-ray system, this design exploits the time-sharing techniques, leading to 31.3% and 29.1% of area reduction in display and decoder parts. Moreover, a graphic and on-screen-display hardwired handshake effectively reduces the DRAM space by 40%. A...
A first-reported, sub-mW/fps/view multi-view video decoder chip fully compliant to 3D Blu-ray specifications is reported. It explores the resource sharing so as to integrate not only single-view MPEG-2/VC-1/AVC but multi-view MVC standards into a single die. Moreover, it features pipeline management and clock management units so as to improve the processing throughput and clock power efficiency. A...
In this paper, a power-aware and low power multimedia processor is presented. A novel clock gating scheme and dynamic frequency selection (DFS) are implemented to minimize the power dissipation and it integrates 7-standards (H.264 / VC1 / RV / AVS / MPEG-1 / MPEG-2 / MPEG-4) with several resource-sharing techniques in both algorithmic and architectural levels so as to achieve significant area and...
The dual-core environment is more and more popular in embedded system recently. The limited buffer and limited bandwidth are critical for parallel algorithm in embedded system. This paper proposes a novel parallel algorithm using functional partitioning with dynamic load balance for video decoder. The video decoding flow of each macroblock is dynamically separated for different cores according to...
In this paper, an AVS-embedded multi-format video decoder is presented. It integrates AVS JP@L6.2, H.264 HP@L4.2, VC-1 AP@L3, and MPEG-2 MP@HL in a single chip and features resources sharing, memory management, and early-stage acqusition to facilitate cost and bandwidth efficiency. For the applications of broadcasting, an adaptive error concealment method is proposed. A chip is fabricated and integrates...
A RF/Servo and backend Blu-ray player SoC providing 3D-rich playback is highly integrated on a 56.25mm2 die in 55nm CMOS. Several cost-effective and high-throughput solutions are realized, leading to 3.85% and 23.13% of area and power reduction. This SoC includes 8× Read, 1080p at 30fps two-view decoding, stereo graphic and HDMI-1.4 output, and dissipates 3.147W from a 1.15/3.3V supply.
The first reported RealVideo-embedded video decoder is presented The embedded streaming (e-Streaming) video decoder integrates RealVideo, MPEG-2, MPEG-4, H.264, and VC-1 by 658 K logic gates and 522 Kbits SRAM. In particular, a RealVideo (RV) is fully-reused and is first integrated into our multi-standard video decoder. It explores RV temporal reference method, RV VLD table reduction, multi-stage...
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