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We present a multi-modulus frequency divider based upon novel dual-modulus 4/5 and 2/3 true single-phase clocked (TSPC) prescalers. High-speed and low-power operation was achieved by merging the combinatorial counter logic with the flip-flop stages and removing circuit nodes at the expense of allowing a small short-circuit current during a short fraction of the operation cycle, thus minimizing the...
This paper presents an original mmW frequency multiplier that provides a 58.32 GHz to 62.64 GHz LO starting from a much lower and fixed frequency of 2.16 GHz. It is composed of a pulsed VCO, which generates equally spaced harmonics in the 60 GHz band, and an injection locked oscillator (ILO) that selects the harmonic of interest. The CMOS 40nm circuit consumes 32 mW and occupies only 0.07 mm2. This...
This paper presents a 8 Gbps high jitter tolerance (JTOL) corner-frequency hybrid CDR that employs blind oversampling phase detector in conjunction with digital proportional integral controller (PIC) for phase/frequency tracking with +/−4000ppm frequency offset compensation over infinite burst. Need of the elasticity buffer has been obviated by using a method of time-varying divider ratios in word-clock...
A CMUT front-end for high performance portable ultrasound medical imaging is proposed. Designed for CMUTs operating in the 1–15 MHz range, it comprises a 100-V TX driver, a high voltage T/R switch and an ultra-low-power RX amplifier. The impact of the large parasitic capacitances of high-voltage devices, responsible for SNR degradation, is minimized by careful design and dedicated circuit techniques...
System-on-a-chip (SoC) applications need multiple power supplies with low noise for analog circuits and high efficiency for digital circuits. Thus, this paper proposes the priority-scheduled program (PSP) for single inductor quad output (SIQO) switching converter to manage energy delivery for four outputs. Consequently, SIQO converter with PSP can provides fast transient response and reduce cross-regulation...
A 64-bit dual-core RISC-V processor with vector accelerators has been fabricated in a 45nm SOI process. This is the first dual-core processor to implement the open-source RISC-V ISA designed at the University of California, Berkeley. In a standard 40nm process, the RISC-V scalar core scores 10% higher in DMIPS/MHz than the Cortex-A5, ARM's comparable single-issue in-order scalar core, and is 49% more...
This paper presents a 79GHz variable gain low-noise amplifier (LNA) and power amplifier (PA), both implemented in 28nm CMOS, and measured at temperatures from 27°C to 125°C. The 4-gain steps LNA and the 17dB gain PA are based on a multistage common source neutralized push-pull topology. The LNA achieves a gain of 23.8dB and a noise figure (NF) of 4.9dB, and the PA achieves a maximum power added efficiency...
A design methodology for interstage and output matching networks for wide-band Power Amplifiers for wireless applications is proposed. Leveraging wideband inductively coupled resonators, we apply Norton transformations for impedance matching. A two-stage differential PA with neutralized common source stages has been realized in 28 nm CMOS using low-power devices. The PA delivers 13 dBm saturated output...
The complexity of the requirements for automotive applications is increasing at an astonishing pace. Concepts from other domains are being introduced in order to address these demands. For example we now need to cover fault tolerant and failsafe systems. The functional safety of systems, products and processes increases with every day and with every new development and we must maintain a grasp of...
A 5th order gm-C filter complete with calibration circuits with wide tuning range and cut-off frequency up to the GHz range is presented. To simplify calibrations, integrators are designed to have a relatively low static gain of 32dB, regulated with negative resistors. Transconductance and gain are continuously controlled with a master-slave approach leading to a remarkably stable filter shape and...
In this paper a 4th-order low-pass continuous-time analog filter is presented. A smart and compact biquadratic cell has been realized using the super-source-follower circuit. The biquadratic cell synthesizes a 2nd-order low-pass transfer function, using only two capacitors and four transistors per stage: two transistors for gm-C transfer function and two transistors as current sources for biasing...
Many Class-C CMOS VCOs have been introduced in the last decade claiming to achieve improved phase noise performance and power efficiency with apparently no tradeoff, however only in the past two years implementation efforts have been focused on stability related issues of such oscillator architectures. In fact, oscillators exploiting time-varying bias techniques may present several stability points...
A complementary p-n class-B oscillator with two magnetically coupled second harmonic tail resonators is presented. For the same oscillation amplitude (constrained by reliability considerations) and the same tank, the p-n oscillator achieves 3–4dB better Figure of Merit (FoM) than an n-only reference one. After frequency division by 2, the p-n oscillator has a measured phase noise that ranges from...
A dynamic range enhanced readout circuit using current subtraction technique is presented for a capacitive touch screen panels. A low-voltage, analog front-end circuit using a high-voltage input signal is implemented. A high voltage (> 10 V) parallel pulse signal is used as the transmitter signal. The receiver system was designed with low voltage (< 5 V). A current-subtraction circuit (CSC)...
This paper describes a 4th-order active-UGB-RC filter using VCO-based amplifiers with zero compensation. The VCO-based amplifier intrinsically has a huge DC gain without the associated stability penalties of conventional multi-stage amplifiers such as reducing unity-gain bandwidth or requiring large area by compensation schemes. By using the large gain of the amplifier, the filter achieves small area...
This paper proposes a LC-VCO with a pulse-driven cross-coupled pair. The proposed pulse driving technique has the ability to achieve class-C like current waveform while reducing the Amplitude-Modulation to Phase-Modulation (A-PM) conversion by parasitic capacitance of the active devices. A VCO is implemented using the proposed technique in a standard 0.18um CMOS technology. It oscillates at a carrier...
This paper presents the co-design of a class-D digitally-controlled oscillator (DCO) and a low-dropout voltage regulator (LDO) generating the supply voltage for the DCO. Despite the high intrinsic supply pushing of the class-D oscillator topology, the LDO noise has only a very marginal impact on the DCO phase noise.
A low-voltage, low-power class-D VCO is presented. An LDO based dynamic supply voltage control technique for the class-D VCO is proposed, which realizes fast and reliable start-up and extremely low-voltage operation of the class-D VCO. The proposed LDO-VCO is fabricated using a 28 nm CMOS technology. The measured phase noise is −115.9 dBc/Hz at 1 MHz offset from the 2.35 GHz carrier, while drawing...
A LC ladder based lowpass filter and programmable gain amplifier is presented for the baseband section of a mm-wave wireless receiver. The filter design combines buffering, filtering and termination in a single stage. Implemented in 180nm CMOS and occupying 0.36mm^2 area, it's measured lowest and highest gain settings are 5.6 and 21.6dB, with corner frequency of 2.3GHz and 1.76GHz, IIP3 of 13.9 and...
We present a low-power high-linearity capacitive harmonic rejection mixer for cognitive radio applications. A passive mixer first receiver with capacitive 16-phase sinusoidal weighting implements harmonic rejection down-conversion, and an AC-coupled fully differential capacitor feedback transimpedance amplifier provides baseband linear voltage gain and band-pass filtering achieving an in-band IIP3...
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