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The following topics are dealt with: IC packaging; CMOS nanoelectronic devices; computing technologies; advances in wireless and multimedia; analog filters; RF synthesizers; low power circuit techniques; bio and emerging applications including MEMS, optical communication, and RFID tag; analog-to-digital converters; wireline communication circuits; image signal processing; memory including DRAM, SRAM,...
Today, as global environmental regulations are being tightened, both IC and package technologies are also becoming far more complicated. More Moore and more than Moore, which manifest themselves in system-on-chip (SoC) and system-in-a-package (SiP), respectively, are being used more in combination to meet the ever-more-stringent cost and time-to-market requirements of consumer products with more functions...
We are facing several difficulties with shrinking LSI chips, such as leakage currents/power consumption, variability, huge costs in R&D and production. Major semiconductor market will be absolutely dependent on further shrinking of Si CMOS transistors with improving transistor structures and lowering drive voltage, increasing wafer diameter and 3D stacking package structures. This way is ??More...
A 2.3 B transistors, 8-core, 16-thread 64-bit Xeon?? EX processor with a 24 MB shared L3 cache was implemented in a 45 nm 9-metal process. Multiple clock and voltage domains are employed to reduce power consumption. Long channel devices and cache sleep mode are used to minimize leakage. Core and cache recovery improve manufacturing yields and enable multiple product flavors using the same silicon...
This paper demonstrates the hard disk drive (HDD) performance improvement by nonvolatile FeRAM cache. First, the 128 Mb ChainFeRAM?? design and power supply system design to meet HDD application are presented. Second, the concept of nonvolatile FeRAM cache and the simulated and measured HDD performance improvement are presented. The read/write bandwidth improvements to 1.12 times, 3.3 times and 1...
Recent advances in silicon photonics bring significant benefits to "macrochip" grids made of arrayed chips. Such configurations have global interconnects long enough to benefit from the high speed, low energy, and high bandwidth density of optics. In this paper we consider the constraints of large macrochip systems, and explore modulator drivers and photodetector receivers that match those...
An 8 Gb/s/link power optimized controller memory interface is implemented in TSMC 40 nm G CMOS process. It is composed of 32 differential data links to support 32 GB/s payload. The bimodal drivers of the request bus enable support of both 12 bits of 2 Gb/s/link single-ended RSL (rambus signaling level) for existing XDRTM memory and 6 bits of 8 Gb/s/link differential signaling for next generation XDR2...
This paper presents the design of a 90 nm 13.56 MHz NFC transceiver. The concept of near field communication is introduced while discussing how a combination of both initiator and target functions are required. The initiator circuitry used to generate the required magnetic field and demodulate the received back-scatter is explained and the passive and active target circuitry used to receive a magnetic...
This paper presents a 1.8 V 300 mW System-In-Package (SiP) solution in mobile S-DMB application. This achieves a 1.8 dB noise figure at 2.6 GHz, while the measured sensitivity is -101 dBm at diversity mode. The SiP is integrated RF tuner, demodulator, SDRAM and other passive components. An internal AGC is integrated for over 100 dB dynamic range. The SiP is 196 pins LFBGA and the size is 10 mm ??...
The first reported RealVideo-embedded video decoder is presented The embedded streaming (e-Streaming) video decoder integrates RealVideo, MPEG-2, MPEG-4, H.264, and VC-1 by 658 K logic gates and 522 Kbits SRAM. In particular, a RealVideo (RV) is fully-reused and is first integrated into our multi-standard video decoder. It explores RV temporal reference method, RV VLD table reduction, multi-stage...
A new linearity improvement technique is proposed to implement a low-distortion Gm-C band-pass filter working in high IF ranges. The purpose of the linearization technique is to eliminate Gm" value of the transconductor by employing a superposition method that combines two opposite non-linear behaviors of the two parallel wings designed inside the transconductor. Instead of conventional biquad...
A discrete-time (DT) anti-alias filter (AAF) with clock-efficient charge-domain filter (CECDF) for high attenuation and bandwidth was developed. This AAF possesses 88.86-dB attenuation and 13-MHz bandwidth at a 600-MS/s input-clock rate (ICR) and a 100-MS/s output-sample rate. The measured gain and IIP3 are 12.2-dB and 0-dBm, respectively, consuming only 5.56-mA from a 1.36-V power supply. The chip...
A low noise, 250-MHz fifth order 0.1 dB ripple Chebyshev gm-C filter, with a novel discrete tuning scheme is presented. The discrete tuning circuit switches ON/OFF small gm cells which are connected in parallel to the main gm cell, based on the PVT conditions, to correct for the shift in the cutoff frequency fc. Compared to conventional tuning schemes, proposed discrete scheme demonstrates improved...
An on-chip capacitor mismatches measurement technique is proposed. The use of a beta-multiplier-biased ring oscillator improves the measurement sensitivity by over 6 times with respect to the state-of-the art. Experimental results using a 90 nm CMOS and thick-oxide transistors are presented. The method enables the measurement of capacitors with mismatches being as small as ?? =0.04% only, and the...
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