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Semiconductor memories are growing in importance as they are now fundamental in every electronic system and offer new manufacturing and development challenges and opportunities. From a manufacturing point of view, the industry has undergone consolidation and today very few players are able to supply the high wafer volumes required by the global market. From a technology development point of view,...
After more than four decades of semiconductor revolution led by CMOS technology, the ability to shrink transistors by 50% every 18 to 24 months is finally coming to an end. For years, the end of transistor scaling, otherwise known as the end of Moore's law, had been prematurely predicted. Case in point just as the industry thought that the fundamental optical wavelength limit would finally inhibit...
Integrated circuits and devices revolutionized particle physics experiments, and have been a cornerstone in the recent discovery of the Higgs boson by the ATLAS and CMS experiments at the Large Hadron Collider at CERN. Particles are accelerated and brought into collision at specific interaction points. Detectors are giant cameras, about 40 m long by 20 m in diameter, constructed around these interaction...
The complexity of the requirements for automotive applications is increasing at an astonishing pace. Concepts from other domains are being introduced in order to address these demands. For example we now need to cover fault tolerant and failsafe systems. The functional safety of systems, products and processes increases with every day and with every new development and we must maintain a grasp of...
The terahertz gap is a roughly decade-wide spectral band geometrically centered at 1THz, for which neither conventional electronics nor room-temperature photonics is particularly well suited. This paper reviews applications that reside in the gap, mapped against the capabilities of various technologies. Lithographic scaling will deliver devices with adequate small-signal performance in the THz band,...
various receiver architectures suitable for SDR and cognitive applications are proposed. To break the traditional noise-linearity-matching trade-off, we offer alternative topologies that are capable of tolerating large blockers without compromising the noise figure. The issues of harmonic rejection and reciprocal mixing are addressed as well and appropriate receiver architectures are highlighted....
Many analog IC designers and students are naturally drawn to ADCs. While some ADC realizations have had a lasting impact including pipelined ADCs with digital redundancy, flash ADCs with folding and interpolation, and multi-bit delta-sigma modulators with dynamic element matching, there are many more recent and emerging ADC design techniques that are receiving much attention and also gaining momentum...
Short Range Radios are predicted to realize a paradigm change by 2020, similar to the revolution of mobile communication, in the nineties. These radios provide the last mile wireless connectivity between “things” and the Internet. They connect your new wearable devices to your smart phone, or enable smart energy monitoring and control in your home. In this paper, we analyze the power breakdown of...
A 16b/250 MS/s ADC employs two time-interleaved ADCs with key mismatch errors calibrated in the analog domain. The ADC achieves 73.4dB SNR and 88dBFS SFDR with a 170MHz input signal. It consumes 750mW power. Die size is 3.5mm × 3.5mm in a 0.18µm CMOS process.
This paper presents a nonlinearity cancellation technique in a closed-loop two-step VCO-based ADC, where the VCO's distortion is substantially mitigated in a robust manner. A dual-input VCO-based quantizer topology is proposed to realize a low-power multi-input adder, with no penalty in terms of nonlinearity. Fabricated in a 40nm CMOS process, the prototype two-step 12-bit ADC achieves 68.7dB/66.8dB...
A 12-bit pipeline ADC with residue amplifiers calibrated for gain and distortion is presented. The settling accuracy of the residue amplifiers was lowered in order to achieve higher energy efficiency, and the resulting errors were corrected in multiple stages using a split-ADC calibration technique. Starting from a typical opamp implementation, the power consumption of the residue amplifier was reduced...
A 50V input range, common-mode and differential, 14bit 2-step SAR ADC is presented. The ADC operating at 250kS/s for a 50VPP input signal on a 15V common-mode voltage achieves 97,8dB SFDR and 80:2dB SNR, while consuming 4.29mW from a single 3.3V supply. The 2-step architecture accomplishes an increase in resolution by reusing conversion residue, with a time-shared configurable amplifier/comparator...
A 7b time interleaved hybrid ADC in 40nm CMOS is presented. The ADC consists of two pipelined stages and combines an intrinsically linear SAR with a fully calibrated binary search architecture to achieve energy efficiency. The first stage of each channel consists of a 3b SAR followed by a dynamic amplifier merged with a comparator. The second stage is a 3b comparator-based asynchronous binary search...
This paper presents a 10-bit, 550-fs step Digital-to-Time Converter (DTC) used in the phase comparison path of a fractional-N, TDC-less and divider-less PLL. The DTC is devised as a single-ended architecture which uses a tunable RC network for delay control. The circuit is optimized for low phase noise not to limit the in-band phase noise performance of the fabricated PLL. Measured INL and DNL are...
A wide tuning range class-B VCO in 28nm CMOS targeted for software defined radio applications demonstrates a technique for minimizing device stress while simultaneously optimizing off-state Q in digitally switched tank capacitor cells. The proposed digital varactor structure can be implemented using only capacitors and NMOS transistors, resulting in a very compact layout. The VCO operates between...
This paper presents a 32kHz input and 960MHz output low-power charge-pump phase-locked loop (CP-PLL) with a novel loop-filter resistor noise reduction technique and reverse sub-threshold leakage compensated source switched charge pump. The resistor noise reduction technique involves no additional active component / power overhead and hence, more beneficial than existing solutions. The PLL with minimum...
A 2 GHz all-digital phase locked loop (ADPLL) with core components operating from a 300-mV supply is presented. Ultra-low voltage frequency division and phase/frequency quantization are performed by a ring oscillator that is superharmonically injection-locked to the digitally-controlled oscillator (DCO). An injection-locking technique is proposed which facilitates locking with no additional active...
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