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A fully-differential capacitive touch sensing method is proposed in which common-mode noise currents are symmetrically subtracted at the differential input of the first stage such that it doesn't contribute to dynamic range reduction in the later stages. And, for better sensitivity, the proposed method could accumulate signal charges in continuous time domain, and does not suffer from aliasing issues...
The first synchronous cyclic TDC is proposed in 28nm CMOS process. A novel 2x time amplifier whose gain is insensitive to variations and noise is proposed by using time conservative nature of the proposed synchronous time adder. The implemented 12b TDC occupies 0.01 mm2, consumes 820µW and it achieves 0.63ps of resolution over 2.6ns of input range.
A Column-Row-Parallel ASIC architecture is proposed to enable 3D wearable / portable medical ultrasound. It offers linear-scaling interconnection, acquisition and programming time, while supporting rich functionality. High voltage MUX in Tx and specially sized source follower in Rx are used to implement parallelization for improved SNR. Fault-tolerant transceiver handles defective transducer elements...
In conventional envelope modulators, a linear regulator is required to attain fast tracking, but it is a significant source of efficiency degradation. To eliminate the linear regulator, a dual-phase switching converter with synchronized adaptive voltage tracking (SAVT) control is employed. The SAVT control enables synchronization and fast hysteretic response for voltage tracking. To overcome the switching...
This paper presents the design, implementation, and nuclear magnetic resonance (NMR) measurements of a wireless, magnetic compliant, implant that increases the signal sensitivity of NMR images by 3.8dB and 2.6dB in 4.7T and 11.1T magnetic field strengths respectively. The device supports sustained reliable operation through a strongly coupled resonance wireless powering scheme in addition to improving...
A first-reported 4K×2K@60fps digital TV SoC processor supporting 9 video formats and integrating HDMI/MHL receiver is fabricated in a 40nm CMOS process. It adopts error compensation processor (ECP) to improve the visual quality, and designs a memory management unit and resource sharing technique to improve the throughput and area efficiency by 38.5% and 34.3%, respectively. Moreover, a lossless compression...
A 23mW, 80MHz BW, 73dB dynamic range continuous-time ΔΣ modulator in 20nm CMOS is presented. The modulator operates from 1.0/1.2/1.5V supplies. Power is minimized by combining a low OSR, fast digital excess loop delay compensation scheme, and several techniques to minimize delay in the feedback path. The result is a highly power efficient modulator that achieves an FOM(DR) of 168dB.
A mixer-less low energy BFSK receiver for wireless sensor networks is presented. Q-enhanced frequency-to-amplitude conversion and linear amplification at RF frequencies provide a large conversion gain and high data rates, leading to improved sensitivity and energy efficiency. Fabricated in a 0.13 µm CMOS process, the 915 MHz receiver, with integrated digital calibration, demonstrates a sensitivity...
A 5.0G-pixel/s readout circuit for 15.3mm×8.6mm optical size, 3.7M-pixel, 1300 fps, and digital output image sensor is presented. To achieve 5.0G-pixel/s readout rate, the high speed column readout circuit is introduced. The novel pixel readout, A/D conversion, and digital data transfer schemes are introduced to realize the readout rate and to reduce the interference noise. The 1 horizontal (1H) readout...
An on-die, lightweight nanoAES hardware accelerator is fabricated in 22nm tri-gate CMOS, targeted for ultra-low power mobile SOCs. Compared to conventional 128-bit AES implementations, this design uses an 8-bit Sbox datapath along with ShiftRow byte-order processing to compute all AES rounds in native GF(24)2 composite-field. This approach along with a serial-accumulating MixColumns circuit, area-optimized...
The real challenge in designing wide-band receivers is the ability to tolerate out of band blockers. In this paper, different blocker rejection techniques are proposed to significantly improve the linearity. The blockers are first rejected prior to the LNA, then, a novel base-band blocker filtering technique further rejects the blockers at the TIA input. A dual mixer architecture is also employed...
We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply.
A novel self-filtering scheme breaks the typical tradeoff between noise and power, enabling a ring oscillator to approach the phase noise performance of an LC oscillator. The prototype N-path filter enhanced voltage-controlled ring oscillator (NPFRVCO) achieves a measured phase noise of −110dBc/Hz at a 1MHz offset frequency for an oscillation frequency of 1.0GHz. The self-clocked N-path filter reduces...
A novel on-chip frequency calibration of temperature dependency is proposed for CMOS reference frequency generator. High-order temperature coefficients are rapidly extracted by employing a carefully designed on-chip heater, so that the frequency deviation due to the temperature variation is accurately estimated, and compensated in digitally by means of all-digital PLL (ADPLL). The proposed technique...
A silicon-photonic link is monolithically-integrated in a bulk CMOS process for the first time. Deep-trench isolation enables polySi waveguide integration. PolySi resonant detectors remove the need for Ge integration. Split-diode design enables half-rate receivers, mitigating transistor speed limitations. An on-chip feedback loop locks the resonant defect detector to the laser wavelength, combating...
This paper reports a combination structure of temperature and voltage sensor in a 16nm FinFET technology. The circuit transforms PTAT voltage across a resistor into an output clock with PTAT pulse-width. Fabricated in a 16nm CMOS, the temperature sensor achieves 1°C resolution over −10 ∼ 90°C range and the voltage sensor achieves 4mV output error over 0.38V to 0.56V. The total chip size is 0.01mm2...
A 1.1 um pitch pixel array fabricated by 45 nm 3D stacked technology, can be switched to peripheral circuits on same wafer or to other stacked wafer for process and signal integrity verification. It supports through silicon connection or direct connection to increase the flexibility by separating pixel array and sensing circuit. The novel wide operation range VCO and low power serializer are implemented...
A hybrid dynamic amplifier is proposed which combines the desirable features of a dynamic amplifier and a class AB amplifier. This technique allows us to achieve a power efficient high resolution pipeline ADC. A proof of concept pipelined ADC in a 0.18 µm CMOS process achieves 74.2 dB SNDR, 87 dB SFDR and 85 dB THD at 30 MS/s. The pipeline ADC consumes 6 mW from a 1.3 V supply and occupies 3.06 mm...
The area efficiency of an inductive-coupling interface is improved by 12 times for WIO2 standard (352Gb/s) and beyond. By using a quadrature phase division multiplexing, coils are overlapped and the density is increased by 4 times. It is further increased by 3 times by shortening communication distance with an ultra-thin fan-out wafer level package. The proposed DRAM/SoC interface at 356Gb/s outperforms...
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