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Background and purpose
Studies assessing the correlations between L‐DOPA‐induced dyskinesias (LIDs) and motor fluctuations with health‐related quality of life (HRQoL) in Parkinson's disease (PD) have yielded conflicting results. This study aimed to assess the relationship between LIDs and motor fluctuations with HRQoL in patients with PD, and to assess the relative contribution of their severity...
This paper discusses the need for on-chip correction of mixed-signal integrated circuits, and particularly Analog-to-Digital Converters (ADCs), for in-situ adaptation to the operating conditions. By operating conditions, we mean the environmental conditions and the electrical settings applied to the ADC by the complex system in which it is implemented. This discussion is supported by experimental...
A promising solution to reduce the testing costs of analog/RF circuits is the alternate test strategy, which permits to replace costly specification measurements by simple low-cost indirect measurements. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is today limited mainly because of a lack of confidence in alternate test predictions. A potential...
A promising solution to reduce the testing costs of analog/RF circuits is the alternate test strategy, which permits to replace costly specification measurements by simple low-cost indirect measurements. This approach has been widely explored and demonstrated in the literature on various case studies over the past twenty years. However it is clear that the efficiency of this strategy strongly depends...
This paper presents a digital on-chip measurement circuit for built-in phase noise evaluation of analog/IF signals. The technique relies on 1-bit acquisition and on-the-fly processing to compute a digital signature related to the phase noise level present in the analog signal. In order to minimize the required hardware resources, the circuit is designed with a semipipeline architecture and modular...
This paper introduces a new technique for low-cost phase noise production testing from 1-bit signal acquisition. The technique relies on reconstruction of phase fluctuation from the binary vector captured by a digital ATE channel. A dedicated post-processing algorithm is developed that permits phase noise evaluation from the analysis of the reconstructed time-domain phase fluctuation. The technique...
This paper presents an embedded test instrument for on-chip phase noise evaluation of analog/IF signals. The technique relies on 1 -- bit signal acquisition and dedicated processing to compute a digital signature related to the phase noise level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources...
This paper introduces a digital method for the evaluation of SSB (Single SideBand) phase noise of analog/RF signals. The technique is based on 1-bit signal acquisition with a digital Automated Test Equipment (ATE) and a dedicated postprocessing algorithm that permits to reconstruct the timedomain phase fluctuations of the analog/RF signal from the captured binary vector. SSB phase noise is then obtained...
In this paper, adaptive tuning strategies for Near Field Communication (NFC) transmitter module are investigated. The objective is to perform auto-adjustment of the matching network associated with the transmitter antenna in order to compensate the influence of the receiver antenna. Two different strategies are studied, aiming at maintaining a constant emitted magnetic field or a constant current...
This paper discusses new implementations of the predictive alternate test strategy that exploit model redundancy in order to improve test confidence. The key idea is to build during the training phase, not only one regression model for each specification as in the classical implementation, but several regression models. This redundancy is then used during the testing phase to identify suspect predictions...
IR-drop effects are increasingly relevant in context of both design and test. We introduce the event-driven simulator MIRID that calculates the impact of IR-drop to the circuit timing. MIRID performs the simulation on two abstraction levels: timing effects in the gate-level net-list, current and voltage waveform propagation in the electrical model of the power-distribution network (PDN). Switching...
The histogram-based technique is commonly used for testing of Analog-to-Digital Converters (ADC). One of the parameters measured thanks to this technique is the Integral Non Linearity (INL). INL is also used as an initial data related to the ADC performances for the computation of a correction table in case of a LUT-based correction technique. In this context of embedded INL measurement and embedded...
An accurate, compact, efficient analytical model at the electrical level of antennas dedicated to NFC (Near Field Communication) applications is presented in this paper. The model takes into account the skin effect, which is usually neglected in existing electrical models while it constitutes a major issue in the NFC context. The proposed model is validated with respect to finite element simulation...
This paper presents a procedure of pre-characterization dedicated to the logic and timing simulation of IR-drop induced delays in a logic Block Under Test (BUT) embedded in a chip. The proposed pre-characterization is twofold: the pre-characterization of the library on the one hand and the pre-characterization of the power grid on the other hand. Both should be computed only once for a given technology...
This paper presents an investigation of two integrated solutions that make a previously developed electrical-only test and calibration procedure, of a MEMS convective accelerometer, realizable on-chip. The idea is to integrate on-chip circuitry that performs all required measurements and evaluates an electrical test parameter on which the test and calibration procedure is based.
In this paper, we explore the use of an adaptive electrical calibration strategy in the context of design-for-manufacturing for MEMS convective accelerometers. The calibration principle relies on the adjustment of the heater power level such that sensitivity is set to a given target value. The idea is to define multiple sensitivity targets in order to improve production yield and to insert a criterion...
This paper concerns production test of analog and RF communication devices. The use of standard digital tester channel for the acquisition of modulated analog/RF signals is investigated in order to implement low-cost functional test. The idea is to use the comparator available in a standard digital test resource to record level-crossing events on a signal coming from the device under test, and then...
MEMS devices are expected to be used in a growing number of high-volume and low-cost applications. However because they typically requires the application of physical test stimuli to verify their specifications, test and calibration costs are actually a bottleneck to reduce the overall production cost of MEMS sensor. This paper presents an alternative electrical-only solution for testing and calibrating...
This paper presents an investigation on the effect of geometrical dimensions on the conductive behaviour of a CMOS MEMS convective accelerometer. Numerous FEM simulations are conducted to prove the validity of a previously developed model. This model was firstly developed to represent the effect of only one geometrical parameter; the etched cavity depth. We prove here that this model may represent...
In this paper, we present an extension of the ANC (“Analogue Network of Converters”)-based method to characterize the harmonic components of a set of converters with random-phase harmonics using only digital test resources. The ANC-based method was primarily developed under the assumption that the harmonics' phase is proportional to the input phase. This assumption is not valid for all converter architectures,...
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